@Copyright 1994
All Rights Reserved.
Manual edition 24, October 1994

The information in this document is subject to change without prior notice in order to improve reliability, design and function and does not represent a commitment on the part of the manufacturer.

In no event will the manufacturer be liable for direct, indirect, special, incidental, or consequential damages arising out of the use or inability to use the product or documentation, even if advised of the possibility of such damages.

This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer.

Trademarks
ACL-7124 is registered trademarks of ADLink Technology Inc., Advantech and PCL-724 are trademark of Advantech Co., Ltd. IBM PC is a registered trademark of International Business Machines Corporation. Intel is a registered trademark of Intel Corporation. Other product names mentioned herein are used for identification purposes only and may be trademarks and/or registered trademarks of their respective companies.



Contents

This manual is designed to help you use the ACL-7124. The manual describes how to modify various settings on the ACL-7124 card to meet your requirements. It is divided into three chapters:

• Chapter 1, "Introduction," gives an overview of the product? features. applications, and specifications.
• Chapter 2, "Installation," describes how to install the ACL-7124. The layout of ACL-7124 is shown, the DIP switch setting for base address, and jumper settings for IRQ level and interrupt status are specified.
• Chapter 3, "Programming," describes how to program the digital input and output ports on the ACL-7124.
• Appendix A, " I/O Port Address Map", specifies the PC's default I/O Port address map.

The ACL-7124 : 24-bit Digital I/O board is a parallel Digital I/O board for IBM PC/XT/AT or compatibles in industrial applications. It is fully hardware and software compatible with Advantech PCL-7124.

This board emulates one industry standard 8255 Programmable Peripheral Interface (PPI) chip, it offers 3 ports: PA, PB, and PC. The PC can also be subdivided into 2 nibble-wide ( 4-bit) ports - PC Upper and PC Low. One 50-pin male ribbon connector comes equipped with the ACL-7124. In addition, two 20-pin connectors, which are corresponding to the 50-pin connector, are also supported for 16-bit digital I/O daughter boards, such as ACLD-782 and ACLD-785.

The ACL-7124 is programmed using simple 8-bit I/O port commands ( inport and outport) or an ACLS-DLL1: digital I/O software driver for high level C language or Windows applications.


1.1 Features

The ACL-7124 24-Bit Parallel Digital I/O Board provides the following advanced features:

• 24 TTL/DTL compatible digital I/O lines
• Emulates one industry standard mode 0 of 8255 PPI
• Buffered circuits for higher driving
• Direct interface with OPTO-22 compatible I/O module
• Programmable interrupt handling
• Output status readback
• Fully hardware and software compatible with Advantech PCL-7124

• Programmable mixed digital input & output
• Industrial monitoring and control
• Digital I/O control
• Contact closure, switch/keyboard monitoring
• Connects with OPTO-22 compatible modules
• Useful with A/D and D/A to implement a data acquisition & control system

This chapter describes how to install the ACL-7124. At first, the contents in the package and unpacking information that you should be careful are described. The DIP switch and jumper settings for the ACL-7124's base address, interrupt IRQ level and interrupt mode and status are also specified.


2.1 What You Have

In addition to this User's Manual, the package includes the following items:

· ACL-7124 24-bit Parallel Digital I/O Card

If any of these items is missing or damaged, contact the dealer from whom you purchased the product. Save the shipping materials and carton in case you want to ship or store the product in the future.


2.2 Unpacking

Your ACL-7124 card contains sensitive electronic components that can be easily damaged by static electricity.

The card should be done on a grounded anti-static mat. The operator should be wearing an anti-static wristband, grounded at the same point as the anti-static mat.

Inspect the card module carton for obvious damage. Shipping and handling may cause damage to your module. Be sure there are no shipping and handing damages on the module before processing.

After opening the card module carton, exact the system module and place it only on a grounded anti-static surface component side up.

Again inspect the module for damage. Press down on all the socketed IC's to make sure that they are properly seated. Do this only with the module place on a firm flat surface.

Note : DO NOT APPLY POWER TO THE CARD IF IT HAS BEEN DAMAGED.

You are now ready to install your ACL-7124.


2.3 ACL-7124's Layout

Figure 2.1 ACL-7124's Layout


2.4 Jumper and DIP Switch Description

You can change the ACL-7124's base address and interrupt by setting DIP switches and jumpers on the card. The card's jumpers and switches are preset at the factory. Under normal circumstances, you should not need to change the jumper settings.

A jumper switch is closed (sometimes referred to as "shorted" with the plastic cap inserted over two pins of the jumper). A jumper is open with the plastic cap inserted over one or no pin(s) of the jumper.


2.5 Base Address Setting

The ACL-7124 requires 4 consecutive address locations in I/O address space. The base address of the ACL-7124 is restricted by the following conditions.

1. The base address must be within the range Hex 200 to Hex 3FF.

2. The base address should not conflict with any PC reserved I/O address. ( refer to Appendix A)

The address setting of the ACL-7124 is described in Table 2.3.

Figure 2.3 Default DIP switch setting

(*) : default setting
X : Don't care
ON = 0 ; OFF = 1
A2, ..., A8 are corresponding to address lines of ISA bus.
A9 is always 1 (OFF).

Table 2.1 Base Address Table

How to Define a Base Address for the ACL-7124 ?
The DIP1 to DIP7 in the switch SW1 are one to one corresponding to the PC bus address line A8 to A2. A9 is always 1; A1 and A2 are always 0. If you want to change the base address, you can only change the values of A2 to A8 ( shadow area of below diagram). Following is an example, which shows you how to define the base address as Hex 2C0.

Base Address : Hex 2C0

The ACL-7124 provides 6 interrupt requests IRQ 2, 3, 4, 5, 6, and 7, which could be set for hardware interrupt generated by, I/O line, PC0 of Port C. The IRQ level is set by jumper J1, refer to figure 2.1 for its location.

One of the three interrupt status of the ACL-7124 ( DIS, PGM, and EN) should be set by jumper J2, please refer to Fig 2.3. The description of these interrupt status are :

DIS : the interrupt capability is always disabled.
EN : the interrupt capability is always enabled.
PGM : programmable interrupt.

If PGM is selected as interrupt status, the interrupt will be enabled when, I/O line, PC4 goes to TTL LOW. If the PC4 goes to TTL HIGH, then the interrupt will be disabled.

Figure 2.3 JP2 Jumper Setting

Two interrupt trigger edges : rising or falling are supported in the ACL-7124. It is selected by jumper J3, see the Fig 2.4 below.

Fig 4.2 J3 jumper setting

A Summary of Interrupt Status

In ACL-7124, the interrupt trigger status are depended on jumper J2, and J3, and, I/O lines, PC0 and PC4. All the possibility of interrupt status are shown in the following table.

J2	J3	PC0	PC4	Interrupt Status
	X	X	X	No Interrupt Request
		L -> H	X	Interrupt Request
		H -> L	X	Interrupt Request
		L -> H	LOW	Interrupt Request
		H -> L	LOW	Interrupt Request
	X	X	High	No Interrupt Request

X : Don't Care
H-> L : Rising Edge Trigger ( from High to Low)
L->H : Falling Edge Trigger ( from Low to High)



2.7 Connector Pin Assignment

The I/O ports of ACL-7124 emulates as one mode 0 Intel 8255 general purpose programmable peripheral interface. Figure 2.4 shows ACL-7124's equally block diagram. One 50-pin connector come equipped with the ACL-7124 board, and it is corresponding to a mode 0 of 8255.

In addition, two 20-pin pin-head connectors are corresponding to the 50-pin connector. These two connectors are used to go with ACLD-785 and ACLD-782, which are 16 bit digital relay output board and digital opto-isolated input board, respectively.

The 50-pin connector's pin assignment is specified in Figure 2.5 below. The two 20-pin connectors' are specified in Figure 2.6 and Figure 2.7, respectively.

Figure 2.4

Figure 2.5 Connector Pin Assignment

· CN 2 : Port A & Port B

Figure 2.6 Pin Assignment of CN2

· CN 3 : Port C

Figure 2.6 Pin Assignment of CN3



3. Programming

The ACL-7124 can emulates MODE 0 of 8255 PPI, and it comes equipped with one 50-pin male IDC connectors that interface with OPTO-22 racks 8, 16, and 24.

The basic function definition of 8255 mode 0 is :

• Two 8-bit I/O ports - PA and PB
• Two nibble-wide ( 4-bit) ports - PC upper and PC lower
• Any ports can be used for both input and output
• Outputs are latched whereas inputs are not latched
• 16 different input/output configurations are available

Two, I/O lines, PC0 is used to generate a hardware interrupt, and PC4 is used to control programmable interrupt.

The I / O of ACL-7124 emulates as one 8255 programmable peripheral interface chip, the control word is to program PA, PB and PC as input port or output port. Table shows the summarize of control word (D0 - D4), and mode states (Mode 0 - Mode 15) .

Table 4.1 Summarize of control word (D0 - D4) and mode state (Mode 0 - Mode 15)


3.2 Register Structure

The ACL-7124 needs 4 bytes of I/O address for I/O operations. The relationship of I/O address and ports' data read / write shows as following table ( Table 4.2), the default base address of below table is 2C0H.

Table 4.2 Ports' I/O address table
(Base Address = 2C0H)


3.3 Interrupt Handling

The ACL-7124 can generate a hardware interrupt to your PC. The following issues should be careful when you want to generate an interrupt trigger.

1. Interrupt IRQ level setting : make sure you already set the right IRQ level by using the jumper J1. Please refer to section 2.7

"interrupt setting".

2. Interrupt trigger status setting :
a. interrupt mode : make sure the jumper J2 is already set as EN or PGM mode.

b. interrupt trigger edge : make sure what kind of edge trigger you need - rising or falling. Please set the jumper J2 for proper interrupt trigger edge.

c. PGM mode: if you choice PGM mode, confirm the ,I/O line, PC4 is kept in TTL LOW status. Otherwise, there is no interrupt trigger will be occurred.

Note : Since the ACL-7124's Input is not latched and no first event trapping is provided to determine which input was active first.

Self Interrupt Trigger
Although the ACL-7124's interrupt signals are normal received from external peripherals. It can also generate a test output signal to emulate an interrupt being inputted from an external device. An example program is shown in the section 3.5 for reference.


3.4 Programming Notes

Before programming the ACL-7124, the following notes will help you more skillful to control the I/O operations through the ACL-7124.

1. Default Input Mode :
After power-on or hardware reset your PC system, all the ports of ACL-7124 are automatically configured as INPUT mode.

2. Output Latch
When an output port is programmed as output mode through control word, it will not affect the connected output device until an output instruction is executed. This means the data will not output until execute the first output instruction.

Figure 3.1 ACL-7124's Signal Direction

3. According the above ACL-7124's signal direction block diagram, some issues should be careful.

a. When a port is set as INPUT or after hardware RESET, its output buffer is Disabled ( high impedance)

b. The output data is lactated in the Output Latch when it is set as OUTPUT mode.

c. When the port is set as OUTPUT, the input circuit is used as an output status read-back.

d. The data in Output Latch is an random value after power on. It has to be initialized before the port to output direction.


3.5 Programming in C language

The following parts are example programs written in C language. The first four parts are just partial programs for your reference, you can not compile them before these programs are complete.

The last program is an example for interrupt handling, you could compile it by Borland C/C++ compiler directly.

1. To initial I/O port

# define BASE 0x2C0     //define base address
# define CWD0 0x80     //0x80 refer to 8255 CW                     

    outportb( BASE + 3 , CWD); 
                     // all ports as output */
    outportb( BASE + 0 , 0x00);
    outportb( BASE + 1 , 0x00);
    outportb( BASE + 2 , 0x00);
                          // PA, PB, and PC as 0x00


2. Write Data to Outport Ports
# define BASE 0x2C0     // define base address
# define PA   0x0      // Port A
# define PB   0x1     // Port B
# define PC   0x2     // Port C
# define CWD 0x80        //ALL output to 8255 CW                     

outportb(BASE + 3,CWD);          //index to CH0 CW
outportb(BASE + PA ,0x23);     // write 23H to PA
outportb(BASE + PB ,0x45);     // write 45H to PB
outportb(BASE + PC ,0xfd);     // write fdH to PC

3. To Read Data from Input Ports

# define BASE 0x2C0     //define base address
# define PA   0x0      // Port A
# define PB   0x1     // Port B
# define PC   0x2     // Port C
# define CWD 0x9B     //ALL input from 8255 CW                     
int pa_data, pb_data, pc_data;

outportb(BASE + 3,CWD);          //index to CH0 CW
pa_d = inportb(BASE + PA); // read from PA
pb_d = inportb(BASE + PB);           // read from PB
pc_d = inportb(BASE + PC);      // read from PC

4. To Read Back from Output Ports

# define BASE 0x2C0     //define base address
# define PA   0x0      // Port A
# define PB   0x1     // Port B
# define PC   0x2     // Port C
# define CWD  0x80     //ALL input from 8255 CW                     
int pa_data, pb_data, pc_data;

outportb(BASE + 3,CWD);          //index to CH0 CW
outport( BASE + PA, 0xaa); // write 0xaa to PA
pa_d = inportb(BASE + PA); // read back from PA
if( pa_d != 0xaa)
{
    printf(" PortA read back error \n");
}

outport( BASE + PA, 0xaa); // write 0xbb to PB
pb_d = inportb(BASE + PB);           // read back from PB
if( pa_d != 0xbb)
{
    printf(" PortB read back error \n");
}

outport( BASE + PA, 0xcc); // write 0xbb to PC
pc_d = inportb(BASE + PC);      // read from PC
if( pa_d != 0xcc)
{
    printf(" PortC read back error \n");
}

5. A Complete Example Program for Interrupt Handling

/****************************************************/
 *  This program deno. how to generate interrupt by *
 *  the ACL-7124 itself.      When you press any key, a   *
 *  beep is generated. When you press ESC key, the  *
 *  system will be quit.                            *
 *                                                       * 
 *  Hardware setting :                              *
 *          Base Address : 0x2C0                         *
 *     IRQ Level    : 2   ( Jumper J1)              *
 *     Int mode     : EN  ( jumper J2)              *
 *     edge trigger : 1-2 ( rising edge)            *
 ****************************************************/

#include <stdio.h>
#include <dos.h>
#include <conio.h>

#define  IRQ2       0x0a
#define  EOI        0x20
#define  BASE_ADDR  0x2c0
#define  PA         0x00
#define  PB         0x01
#define  PC         0x02
#define  CW         0x03


void interrupt isr_7124()
{
    printf("\7");            // beep
    outportb( 0x20, EOI);    // EOI of 8259
}

main()
{
    int  mask, keyin;
    void interrupt (*old_irq2_isr)();

    old_irq2_isr = getvect( IRQ2);
    setvect( IRQ2, isr_7124);
    mask = inportb( 0x21);

         outportb( BASE_ADDR + CW, 0x80);  // set PA, PB and PC                                     
                                      // as output mode
         clrscr();                         // clear screen

    printf( " press <ESC> to QUIT \n");
    do
    {
       keyin = 0;
       printf(" press any key to genetate an interrupt 
                except <ESC>\n");
       keyin = bioskey(0);

       outportb( 0x21, 0xbf & mask); // IRQ2 nonmasked

       outportb( BASE_ADDR + PC, 0x00);
       delay( 100);
       outportb( BASE_ADDR + PC, 0x01);

    } while( (keyin & 0xff) != 27); // QUIT when ESC pressed

    setvect( IRQ2, old_irq2_isr);   // restore old isr
    outportb( 0x21, mask);          // restore 8259 mask
}

Seller warrants that equipment furnished will be free form defects in material and workmanship for a period of one year from the confirmed date of purchase of the original buyer and that upon written notice of any such defect, Seller will, at its option, repair or replace the defective item under the terms of this warranty, subject to the provisions and specific exclusions listed herein.

This warranty shall not apply to equipment that has been previously repaired or altered outside our plant in any way as to, in the judgment of the manufacturer, affect its reliability. Nor will it apply if the equipment has been used in a manner exceeding its specifications or if the serial number has been removed.

Seller does not assume any liability for consequential damages as a result from our products uses, and in any event our liability shall not exceed the original selling price of the equipment.

The equipment warranty shall constitute the sole and exclusive remedy of any Buyer of Seller? equipment and the sole and exclusive liability of the Seller, its successors or assigns, in connection with equipment purchased and in lieu of all other warranties expressed implied or statutory, including, but not limited to, any implied warranty of merchant ability or fitness and all other obligations or liabilities of seller, its successors or assigns.

The equipment must be returned postage-prepaid. Package it securely and insure it. You will be charged for parts and labor if you lack proof of date of purchase, or if the warranty period is expired.

©1995 Circuit Specialists, Inc.