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Trademarks
ACL-7130 is registered trademarks of ADLink Inc., IBM PC is a registered trademark of International Business Machines Corporation. Intel is a registered trademark of Intel Corporation. Other product names mentioned herein are used for identification purposes only and may be trademarks and/or registered trademarks of their respective companies.

Contents

This manual is designed to help you use the ACL-7130. The manual describes how to modify various settings on the ACL-7130 card to meet your requirements. It is divided into six chapters:

• Chapter 1, "Introduction," gives an overview of the product features, applications, and specifications.
• Chapter 2, "Installation & Configuratinos" describes the operation method and multi-functions of the ACL-7130. Users should read through this chapter to understand the configurations of the ACL-7130 and to understand how to install the ACL-7130.
• Chapter 3, "Register Format," describes the details of register format of the ACL-7130, this information is very useful for the programmers who want to control the hardware by low level programming.
• Chapter 4, "Signal Connection & Applications," describes the conectors' pin assignment and how to connect the outside signal and devices with the ACL-7130. Some applications also be introduced.
• Chapter 5, "High-level Programming," introduces the C-language library for operating the ACL-7130.

The ACL-7130 is an isolated digital I/O card. It is a compact-size add-on card for IBM AT compatible PC. The card provides 16 isolated input and 16 isolated output channels. The isolated channels are suitable for applications in the industry environment. There are another 16 non-isolated digital input and output channels. It lets users to use the card more flexable.

The card provides dual interrupt lines. One is generated by the external digital signals and the other is generated from the 8254 timer. The dual interrupt lines are very usable in industrial applications of watchdog and trigger signal monitoring.

This card provides one 8254 chips on board. Two 8254 counters are cascaded to provide a timer interrupt source. The another counter can be freely used by users.

The I/O signals are via a 37 pin D-type connector that project through the computer case at the rear of the board. The figure 1.1 shows the block diagram of the ACL-7130.


1.1 Features

The ACL-7130 isolation digital I/O card provides the following advanced features:

• 16 isolated digital input and output channels
• 16 non-isolated digital input and output channels
• One 8254 chip one board which provide a set of cascaded timers and one independent counter
• Dual interrupt channels, one is for external interrupt and the other is for on board timer interrupt.
• Fully backward compatible with PCL-730
• Use 37-pin D-type female connector.
• AT-Bus and Compact / Half size PCB

• Laboratory and Industaial automation
• Watchdog timer
• Event counter
• Frequency counter and generator
• Low level pulse generator
• Time delay
• Industry automation

¨ Isolated Digital Output

• # of channels : 16 channels
• Electronical characteristics : Open collector transister

• # of channels : 16 channels
• Electronical characteristics : Non-polarity photo-coupler

• Device : 8254
• Counters : 16-bit counter
• Clock source : internal clock, external source or cascaded
• Gate control : default enable or external control

• I/O Base Address : 8 consecutive address space
• Interrupt IRQ : IRQ 3,4,5,6,7 for external digital interrupt IRQ 9,10,11,12,15 for internal timer interrupt
• Connector : 37-pin D-type female connector
• Operating Temperature : 0° C ~ 60° C
• Storage Temperature : -20° C ~ 80° C
• Humidity : 5 ~ 95%, non-condensing
• Power Consumption : +5 V @ ??? mA maximum
• Dimension : 160(?)mm(L) X 124(?)mm(W)

This chapter describes the configurations and multi-functions of the ACL-7130 and teach users to install the ACL-7130. At first, the contents in the package and unpacking information that you should care about are described. The verstile configurations of ACL-7130 are introduced so that you can configure it according to your applications. The default setting of ACL-7130 is shown at the end of this chapter.


2.1. What You Have

In addition to this User's Manual, the package includes the following items:

• ACL-7130 Ehanced Multi-function Data Acquisition Card
• Utility & Library Diskette
• ACL-7130 Software Utility

If any of these items is missing or damaged, contact the dealer from whom you purchased the product. Save the shipping materials and carton in case you want to ship or store the product in the future.


2.2. PCB Layout of ACL-7130

Figure 2.1 PCB Layout of the ACL-7130


2.3. Jumper and DIP Switch Description

You can change the ACL-7130's default configuration by setting jumpers and DIP switches on the card for your own applications. The card's jumpers and switches are preset at the factory. A jumper switch is closed (sometimes referred to as "shorted") with the plastic cap inserted over two pins of the jumper. A jumper is open with the plastic cap inserted over one or no pin(s) of the jumper.


2.4. Base Address Setting

The ACL-7130 requires 8 consecutive address locations in the I/O address space. The base address of the ACL-7130 is restricted by the following conditions.

1. The base address must be within the range Hex 200 to Hex 3FF.
2. The base address should not conflict with any PC reserved I/O address.
3. The base address must not conflict with any add-on card on your own PC. Please check your PC before installing the ACL-7130.

The ACL-7130's base address of registers is selected by an 6 positions DIP switch SW1. The default setting of base address is set to be HEX 280. All possible base address combinations are listed as Table 2.2. You may modify the base address if the address HEX 280 has been occupied by another add-on card.

A3 ~ A8 control the BASE I/O address.

Figure 2.2 Default Base Address Setting

* A3, ..., A8 is corresponding to PC Bus address lines

Table 2.1. Possible Base Address Combinations


2.5. Pin Assignment of DIO Connectors

There are three DIO connector. The pin assignment of the 37 pins D-type connector CN1, which is an isolated DIO signal connector, is shown in Figure 2.3. The definitions of the non-isolated DIO signal connectors CN2 and CN3 are shown is Figure 2.4 and Figure 2.5 respectively.

Legend:
IDI_n : Isolated digital input channel #n
IDO_n : Isolated digital output channel #n
EIGND : Ground return path of isolated input channels
EOGND : Ground return path of isolated output channels
VDD : Power supply of isolated output channels
Figure 2.3. Pin assignment of Connector CN1

· CN 2: Digital Signal Input (DI 0 - 15 )

Figure 2.4. Pin assignment of Connector CN2

· CN 3: Digital Signal Output (DO 0 - 15 )

Figure 2.5. Pin assignment of Connector CN3

Legend :
DO n : Digital output signal channel n
DI n : Digital input signal channel n
GND : Digital ground



2.6. Setting of Lower IRQ Levels (JP1)

2.7. Setting of Higher IRQ Levels (JP2)

2.8. Setting of Lower IRQ Signal Source (JP3)

2.9. Setting of Lower IRQ Signal Polarity (JP4)

2.10. Counter Signals Connector (JP5)

There is an internal programmable timer/counter 8254 chip on the ACL-7130. The counter1 and counter 2 are cascaded together for timer pacer generation. The reminder counter 0 are available for flexible usage. The jumper JP5 is connector for counter 0 and its pin assignment is illustrated as figure 2.10.

Figure 2.10 Pin Assignment of JP5

The pacer rate of above configuration is determined by the formula: pacer rate = 2 MHz / (C1 * C2)

The maximum pacer signal rate is 2MHz/1=2MHz. The minimum signal rate is 2MHz/65535/65535, which is very slow frequency that user may never use it. For example, if you wish to get a pacer rate 2.5 KHz, you can set C1 = 40 and c2 = 20. That is 2.5KHz = 2MHz / (40x20).



3. Registers Format

This chapter describes details of the register format of the ACL-7130. This information is quite useful for the programmer who wish to handle the card by low-level program.

In addition, the low level programming is introduced. This imformation can help the beginners to manipulate the ACL-7130 in the shortest learnning time.


3.1. I/O Port Address

The ACL-7130 requires 8consecutive addresses in the PC I/O address space. The I/O address map is compatible with PCI-730 but whith one more timer / counter chip. Table 3.1 shows the I/O address of each register with respect to the base address.

There are total 32 digital input channels on the ACL-7130, including 16 isolated DI channels and 16 non-isolated channels. Each bit is corresponding to a signal on the connector.

Address : BASE + 0 ~ BASE + 3

Attribute : read only

Data Format :

There are total 32 digital output channels on the ACL-7130, including 16 isolated DO channels and 16 non-isolated channels. Each bit is corresponding to a signal on the connector.

Address : BASE + 0 ~ BASE + 3

Attribute : write only

Data Format :

The 8254 occupies 4 I/O address locations in the ACL-7130 as shown blow. Users can referr to NEC's or Intel's data sheet for a full description of the 8253 features, condensed information is specified in Appendix B.

Address : BASE + 4 ~ BASE + 7

Attribute : read / write

Data Format :

To manipulate the ACL-7130, users may understant how to write a hardware depedent low-level program. The low-level programming can be carried out by using either assembly or high-level language such as BASIC or C language. The following gives examples to show how to use programming language to access a DAS card or any add-on I/O card.

Getting Started

Before programming, the add-on card should be correctly installed. After installing the card, the users should already understand how much system (PC) resources are used by this card, such as I/O address, IRQ channels, and even DMA channel, etc.

The second step is to study the register format and the operation theorem of the card. Then users can try to write low-level programs to operate it. Although the high-level program library is available, the low-level programming can improve the efficiency and perform functions which the library does not support. The low level programming is not difficult and may be necessary to understand.

Programming Language

The programming language to be used is dependent on users' familarity and the system requirement. No matter what kind of language is used, the user must understand the syntax of the I/O instructions to acdess the I/O card. The following sections introduce the syntax of the often used programming laguages. In each section, the write (output) port instruction and the read (input) port instruction are shown. In the examples, the base address of the I/O card is assume as HEX 240 and the port of the register to be access is BASE+2.

Assembly

To write an output port:
      out     280h,value
      out     280h,register
 
 To read an input port
      in     A, 280h
 BASIC language
 To write an output port:
      10     BASE=&H280
      20      VALUE% = &H2F
      30     OUT( BASE+2), VALUE %
             or
      10     OUT( &H282 ), &H20
 
 To read an input port
      10     BASE=&H280
      20     VALUE=INP( BASE+2)
             or
      10     VALUE=INP( &H282 )
 C language (Borland C++)
 To write an output port:
      #define      BASE     0x280
      unsigned int     Value=0x2F;
      outportb( BASE+2 ,  Value );
           or
      outportb( 0x242 ,  0x2F );
 
 To read an input port
      #define      BASE     0x280
      unsigned int     Value;
      Value = inpportb( BASE+2 );
           or
      Value = inportb( 0x242 );
 C language (MicroSoft C)       (????????????????????)
 To write an output port:
      #define      BASE     0x240
      unsigned int     Value=0x2F;
      outp( BASE+2 ,  Value );
           or
      outp( 0x242 ,  0x2F );
 
 To read an input port
      #define      BASE     0x240
      unsigned int     Value;
      Value = inp( BASE+2 );
           or
      Value = inp( 0x242 );
	  

Perform Functions

Users should study the operation theorem and the relative data sheet to understand how to operate this card, then use the low-level programming to perform those functions. Gererally, the DIO control can be easily performmed by only a few instructions, it is very suitable to use the low level programming.

As to the higher level functions such as the the interrupt service routines, the DMA control, the FIFO buffer control, etc, user may use the library or modify the examples to carry them out. However, fully understanding of the PC system is necessary for certain applications.



Appendix. Timer/Counter Operation

The ACL-7130 has one 8254 chip on board. Refer to section 3.5 for the signal connection and the configuration of the counters. The following sections describe the details of the 8254 chip.

The 8254 Timer / Counter Chip

The Intel (NEC) 8254 contains three independent, programmable, multi-mode 16 bit counter/timers. The three independent 16 bit counters can be clocked at rates from DC to 5 MHz. Each counter can be individually programmed with 6 different operating modes by appropriately formatted control words. The most commonly uses for the 8254 in microprocessor based system are:

• programmable baud rate generator
• event counter
• binary rate multiplier
• real-time clock
• digital one-shot
• motor control

For more information about the 8254 , please refer to the NEC Microprocessors and peripherals or Intel Microsystems Components Handbook.

Timer Interrupt Source

The counter 1 and counter 2 are cascaded together to generate the timer interrupt. The frequency is software controllable. The maximun pacer signal rate is 2MHz/4=500K and the minimum signal rate is 2MHz/65535/65535, which is a very slow frequency that user may never use it.

General Purpose Timer/ Counter

The counter 0 is free for users' applications. The clock source, gate control signal and the output signal is send to the connector JP5. The general purpose timer / counter can be used as event counter, or used for measuring frequency, or others functions. See the `Timer/Counter Applications' section for examples.

I/O Address

The 8254 in the ACL-7130 occupies 4 I/O address as shown below.

The programming of 8254 is control by the registers BASE+4 to BASE+7. The functionality of each register is specified this section. For more detailed information, please refer handbook of 8254 chip.

Control Byte

Before loading or reading any of these individual counters, the control byte (BASE+3) must be loaded first. The format of the control byte is :

· SC1 & SC0 - Select Counter ( Bit7 & Bit 6)

· RL1 & RL0 - Select Read/Load operation ( Bit 5 & Bit 4)

· M2, M1 & M0 - Select Operating Mode ( Bit 3, Bit 2, & Bit 1)

· BCD - Select Binary/BCD Counting ( Bit 0)

Mode Definitions

In 8254, six operating modes can be selected. they are :

• Mode 0 : Interrupt on Terminal Count
• Mode 1 : Programmable One-Shot.
• Mode 2 : Rate Generator.
• Mode 3 : Square Wave Rate Generator.
• Mode 4 : Software Triggered Strobe.
• Mode 5 : Hardware Triggered Strobe.

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