32 digital output channels can be write and readback from this register

Address : BASE + 14
Attribute : READ/WRITE
Data Format :

The digital output status can be readback through the location (BASE + 14)

3.1.3 DIO Status & Control Register ( BASE + 18 )

The data transfer mode of digital input is controlled and status is checked through this register.

Address : BASE + 18
Attribute : READ/WRITE
Data Format :

¨ Digital Input Mode Setting :

I_ACK  : Input ACK Enable
      1 : Input ACK is enabled ( input ACK will be asserted 
                  after input data is read by CPU or written to input FIFO)
      0 : Input ACK is disabled
 
           I_REQ  : Input REQ Strobe Enabled
              1 : Use I_REQ edge to latch input data
      0 : I_REQ is disabled
 
           I_TIME0 : Input Counter 0  Enable
             1.    input is sampled by falling edge of Counter 0 output  
                  ( COUT0)
      0 : Input Counter 0 is disabled
      
      I_FIFO : Input FIFO  Enable Mode
      1 : Input FIFO is enabled
              ( input data is saved to input FIFO)
      0 : Input FIFO is disabled
 
           TRGPOL : Input Trigger Polarity
      1 : I_TRG is Rising Edge Active
      0 : I_TRG is Falling Edge Active
      
      W_TRG : External Trigger Enable
      1 : wait until I_TRG signal is active
                   Digital input sampling will begin after a rising or falling 
                   edge of I_TRG is comming.
      0 : start input sampling immediately 
                   ( if input control register is set)
           DIN_EN : Digital Input Enable
      1 : Digital Input Enable
      0 : Digital Input Disabled
                   When this bit is set as 0, all digital input operation will 
                   be stopped.
      
 ¨    Digital Output Mode Setting :
 
 O_ACK  : Output ACK Enable
      1 : Output ACK is enabled, the output circuit will wait for 
                   O_ACK after O_REQ strob is asserted. 
      0 : Output ACK is disabled
 
           O_REQ  : Output REQ Enable
      1 : Output REQ is enabled, an O_REQ strobe will be
                   generated after output data is strobe
      0 : Output REQ is disabled
 
           O_TIME1 : Output Counter 1  Enable
      1 : Output Counter 0 is enabled, output data is moved 
                   from output FIFO to DO registers ehen output of 
           Counter1 goes low.
      0 : Output Counter 0 is disabled
      
      O_FIFO : Output FIFO  Enable
      1 : Output FIFO  is enabled
              ( output data is moved from output FIFO)
      0 : Output FIFO is disabled
      
      O_TRG : Digital Output Trigger Signal
              This bit is used to control the pin-36 of CN1, when 
      1 : pin-36 of CN1 will go High (1)
      0 : pin-36 of CN1 will go Low (0)
 
 ¨    Digital I/O FIFO Status :
 
 I_OVR : Input data over-run
      1 : Digital Input FIFO is full ( over-run)
      0 : No input data over-run occured
 Input data over-run occured, the I_OVR bit is set when input FIFO is full and ther is new input data comming in. The is bit can be cleared by writing 
"1" to it.
 
 O_UND : Output data FIFO is under-run
      1 : Output FIFO is empty
           0 : No output data under-run occured
		   

Output data under-run, the O_UND bit is set when output FIFO is empty and the output request for new data, this bit can be cleared by writing "1" to it.

3.1.4 Interrupt Status & Control Register ( BASE + 1C )

The interrupt modes are control and its status are checked through this register.

Address : BASE + 18
Attribute : READ/WRITE
Data Format :

¨ Interrupt Trigger Control :

In PCI-7200, the interrupt can be triggered by many signal sources, such as O_ACK, I_REQ, TIME 0, TIME 1, and TIME 2. The interrupt trigger source is controlled by the following register :

IO_ACK : Interrupt is triggered by O_ACK signal
              1 : IO_ACK interrupt is enabled
                                  0 : IO_ACK interrupt is disabled
 
 II_REQ : Interrupt is triggered by I_REQ      signal
              1 : II_REQ interrupt is enabled 
              0 : II_REQ interrupt is disabled
 
 
 T0_EN : Interrupt is triggered by TIME 0
              1 : T0_EN interrupt is enabled 
              0 : T0_EN interrupt is disabled
 T1_EN : Interrupt is triggered by TIME 1
              1 : T1_EN interrupt is enabled 
              0 : T1_EN interrupt is disabled
 T2_EN : Interrupt is triggered by TIME 2
              1 : T2_EN interrupt is enabled 
              0 : T2_EN interrupt is disabled
 
 ¨    Interrupt Trigger Status :
 In PCI-7200, the interrupt can be triggered by many signal sources, such as O_ACK, I_REQ, TIME 0, TIME 1, and TIME 2. The following bits are 
used to check interrupt status:
 
 SO_ACK : Status of  IO_ACK
                   1 : Interrupt is triggered by O_ACK signal
              0 : No IO_ACK interrupt
 SI_REQ : status of  I_REQ     
              0 : No I_REQ Interrupt 
              1 : Interrupt is triggered by I_REQ signal
 
 SI_T0 : Status of  T0_EN
              0 : No T0_EN Interrupt 
              1 : Interrupt is triggered by OUTO ( output of TIME 0)  
                   signal
 SI_T1 : Status of  T1_EN
              0 : No T1_EN Interrupt 
              1 : Interrupt is triggered by OUT1 ( output of TIME 1)  
                   signal
 SI_T2 : Status of  T2_EN
              0 : No T2_EN Interrupt 
              1 : Interrupt is triggered by OUT2 ( output of TIME 2)  
                   signal
 
 ¨    Timer Configuration Control  :
 The 8254 timer on the PCI-7200 can be configured as either COUNTER2 cascaded COUNTER 0 or COUNTER2 cascaded COUNTER 0. These 
timer configuration is controlled by the following register.
 
 T0_T1 :  COUNTER0 is cascaded with COUNTER 2
           1 : COUNTER2 and COUNTER 0 are cascaded together
           0 : No cascaded
 
 T0_T1 :  COUNTER1 is cascaded with COUNTER 2
           1 : COUNTER2 and COUNTER 1 are cascaded together
           0 : No cascaded
 
 ¨    I_REQ Polarity Selection  :
 When the input samling is controlled by the I_REQ signal only, the I_REQ can be programmed to be rising edge active or falling edge active.
 
 REQ_NEG :  I_REQ trigger polarity
           1 : latch input data on falling edge of I_REQ
           0 : latch input data in rising edge of I_REQ
		   

In ACL-7200, there are four data transfer modes can be used for digital I/O access and control, these modes are :

1. Direct Program Control : the digital inputs and outputs can be access and control by its corresponding I/O port address directly.

2. Internal Timer Pacer Trigger : the digital input and output operations are handled by internal timer pacer trigger and transferred by bus mastering DMA.

3. External Trigger : the digital input and output operations are handled by external I/O strobe and transferred by bus mastering DMA.

4. Handshaking : through REQ input signal and ACK output signal, the digital I/O can have simple handshaking data transfer.

The digital I/O operations can be controlled by I/O port BASE+10 for digital input and BASE+14 for digital output.

The I/O port address BASE is assigned by system BIOS, please refer to Section 5 for more detailed description.

The digital OUT operation is :

    outport(  BASE+14, 0xAAAA )   // ( A : 0 ~ F)

The digital IN operation is :
 
    value = inport( BASE+10)         // The input status is save in the 					// value variable

The digital I/O access control is triggered by timer pacer which is generated by a interval programming timer/counter chip 8254. There are three counters on the 8254, the counter 0 is used to generate timer pacer for digital input, and counter 1 is used for digital output. The configuration is illustrated as below.

The operations sequence are :

1. Define the frequency ( timer pacer rate)

2. The digital input data are saved in FIFO after a timer pacer is generated. The sampling is controlled by timer pacer.

3. The data saved in FIFO will transfer to main memory of your computer system directly and automatically. This is controlled by bus mastering DMA control, this function is supported by PCI controller chip.

The operation flow is show as below :



4.3 External Trigger

The digital input access control is triggered by external strobe, which is from the pin-19 I_ACK of CN1. The operation sequence is very similar to Timer Pacer Trigger. Their difference is trigger source is from differenct devices.

1. The external input strobe is generated from outside device, and go through the Pin 19 ( I_ACK ) of CN1 and to trigger the digital input operations.

2. The digital input data are saved in FIFO after an I/O strobe signal is comming in.

3. The data saved in input FIFO will transfer to main memory on your computer system directly. This is controlled by bus mastering DMA control, this function is supported by PCI controller chip.

4.4 Handshaking

In PCI-7200, it also supports a handshaking digital I/O transfer mode. That is, after input data is ready, a INREQ is sent form external device, and INACT will go high to acknowledge the data already accessed.

I_REQ & I_ACK for Digital Input
1. Digital Input Data is ready
2. an I_REQ signal is generated for digital input operation
3. digital input data is saved to FIFO
4. an I_ACK signal is generated and sent to outside device
5. If the FIFO is not empty and PCI bus is not occupied, the data will be transferred to main memory

O_REQ & O_ACK for Digital Output

1. Digital Output Data is moved from PC memory to FIFO of PCI-7200 by using DMA data mastering data transformation.

2. Move output data from FIFO to digital output circuit

3. output data is ready

4. an O_REQ signal is generated and sent to outside device

5. After an O_ACK is got, the step 2 to step 5 will be repeated again.

** if the FIFO is not full, the output data is moved form PC`s main memory to FIFO automatically.

4.5 Timing Characteristic

1. I_REQ as input data strobe ( Rising Edge Active)

2. I_REQ as input data strobe( Falling Edge Active)

3. I_REQ & IN_ACK Handshaking

Note : I_REQ must be asserted until I_ACK asserts, I_ACK will be asserted until I_REQ deasserts.

4. O_REQ as output data strobe

5. O_REQ & OUT_ACL Handshaking

Note : O_ACK must be deaserted before O_REQ asserts, O_ACK can be asserted any time after O_REQ asserts, O_REQ will be deasserted after O_ACK is asserted.



5. C/C++ & DLL Libraries

In this chapter, the PCI-7200's two software drivers : C/C++ language library for DOS and DLL driver for Windows 3.11, Win-95 and Win-NT are described.


5.1 Installation

5.1.1 Backup Your Disk

The Utility Software and Library supplied with PCI-7200 are in DOS format which is compatible with DOS 3.0 or higher reversions. It is advisable to make a back up copy before using the software.

For a direct back up, use the DOS DISKCOPY or alternatively XCOPY *.* to a pre-formatted disk. The back up procedures are specified as follows:

1. Insert "Utility and Library" Diskette into floppy drive A:

2. XCOPY a:*.* b:/s

5.1.2 Installation

The PCI-7200's Utility Diskette includes a utility software,

C-language library, DLL libraries and some demonstration programs which can help you reduce programming work and support the calibration of analog inputs and outputs.

Due to the installation on different O.S. platforms should follow different procedures. The installation procedures are classified to four O.S..

¨ MS-DOS Installation :

You will need to manually copy the contents of diskette to your hard disk. The procedures should be followed as :

1. Turn your PC's power switch on
2. Put the " PCI-7200 Utility & Library " diskette into your floppy drive A: or B:
3. Install for DOS environment
A\> CD\DOS
A:\DOS> SETUP
¨ MS-Windows 3.11 Installation :
Install for WINDOWS 3.11 environment
execute a:\WIN-31\SETUP.EXE
¨ Win- 95 Installation :
Install for WIN-95 environment
execute a:\WIN-95\SETUP.EXE

( PCI-7200 is a plug & play, so please following the standard Win-95 convention to install hardware driver. This driver is included in this diskette.)

¨ Win- NT Installation :
Install for WIN-NT environment
execute a:\WIN-NT\SETUP.EXE



5.2 Running Testing Utility ( 7200UTIL.EXE)

After finishing the installation, you can execute the utility by typing as follows :

C> cd \7200\DOS\UTIL

C> 7200UTIL

the following diagram will be displayed on you screen.


5.3 Software Driver Naming Convention

The functions of PCI-7200's software drivers are using full-names to represent the functions' real meaning. The naming convention rules are :

In DOS Environment :

_{hardware_model}_{action_name}. e.g. _7200_Initial ().

In order to recognize the difference between DOS library and Windows library, A capital "W" is put on the head of each function name of the Windows DLL driver. e.g. W_7200_Initial ()

There are 20 function calls provided by each driver for PCI-7200 Digital I/O cards; all drivers ( DOS, Win-31, Win-95 and Win-NT) provide the same function capability. The function names using in Windows is only a capital "W" is put on the head of each function name of DOS library.

The detailed description of each function are specified in the following sections.


5.4 _7200_Initial

@ Description

A PCI-7200 card is initialized according to the card number. Because the PCI-7200 is PCI bus architecture and meets the plug and play design, the IRQ and base_address ( pass-through address) are assigned by system BIOS directly.

Every PCI-7200 card has to be initialized by this function before calling other functions.

Note : Because configuration of PCI-7200 is handled by the system, there is no jumpers or DMA selection on the PCI boards that need to be set up by the users.

@ Syntax
Visual C++( Windows 3.11, Win-95, and Win-NT)
int W_7200_Initial(U8 card_number, U16 *base_addresss,     U8 *irq_no )

Visual Basic (Windows 3.11, Win-95, and Win-NT)
int W_7200_Initial( ByVal card_number as Byte, base_addresss as Integer, irq_no as Byte ) As Integer

C/C++ ( DOS)
int _7200_Initial(U8 card_number, U16  *base_addresss,        U8  *irq_no )

@ Argument :

card_number :	 the card number to be initialized, only four   cards 				can be initialized, the card number must be CARD_1, CARD_2, CARD_3  or CARD_4.

base_address : the I/O port base address of the card, it  is  assigned by system BIOS.

irq_no               : system will give an available interrupt number to this card automatically.


@ Return Code :

ERR_NoError
ERR_InvalidBoardNumber
ERR_PCIBiosNotExist
ERR_PCICardNotExist
ERR_PCIIrqNotExist
ERR_BaseAddressError

@ Description

After initialized more than one PCI-7200 cards, this function is used to select which card is used currently.

@ Syntax

Visual C++( Windows 3.11, Win-95, and Win-NT) int W_7200_Switch_Card_No(U8 card_number)

Visual Basic (Windows 3.11, Win-95, and Win-NT) int W_7200_Switch_Card_No( ByVal card_number as Byte )As Integer

C/C++ ( DOS)

int _7200_Switch_Card_No(U8 card_number)

@ Argument :

card_number : The card number to be initialized, only two cards can be initialized, the card number must be CARD_1, CARD_2, CARD_3 or CARD_4;

@ Return Code :

ERR_NoError
ERR_InvalidBoardNoInit


5.6. _7200_DI

@ Description

This function is used to read data from digital input port. There are 32-bit digital inputs on the PCI-7200. You can get all 32 input data from _7200_DI by using this function.

@ Syntax

Visual C++( Windows 3.11, Win-95, and Win-NT) int W_7200_DI ( U32 *di_data)

Visual Basic (Windows 3.11, Win-95, and Win-NT) int W_7200_DI( di_data as Long )As Integer

C/C++ ( DOS) int _7200_DI( U32 *di_data )

@ Argument :

di_data : return all 32-bit value from digital port.

@ Return Code :

ERR_NoError


5.7 _7200_DI _Channel

@ Description

This function is used to read data from digital input channels (bit). There are 32 digital input channels on the PCI-7200. When performs this function, the digital input port is read and the value of the corresponding channel is returned.

* channel means each bit of digital input ports.

@ Syntax

Visual C++( Windows 3.11, Win-95, and Win-NT) int W_7200_DI_Channel (U8 di_ch_no, Boolean *di_data)

Visual Basic (Windows 3.11, Win-95, and Win-NT) int W_7200_DI_Channel ( ByVal di_ch_no as Byte, di_data as Boolean )As Integer

C/C++ ( DOS) int _7200_DI_Channel( U8 di_ch_no, Boolean *di_data )

@ Argument :

di_ch_no : the DI channel number, the value has to be set from 0 to 31.
di_data : return value, either 0 or 1.

@ Return Code :

ERR_NoError
ERR_InvalidDIChannel


5.8 _7200_DO

@ Description

This function is used to write data to digital output ports. There are 32 digital outputs on the PCI-7200,

@ Syntax

Visual C++( Windows 3.11, Win-95, and Win-NT) int W_7200_DO (U32 do_data)

Visual Basic (Windows 3.11, Win-95, and Win-NT) int W_7200_DO ( ByVal do_data as Long )As Integer

C/C++ ( DOS) int _7200_DO(U32 do_data )

@ Argument :

do_data : value will be written to digital output port

@ Return Code :

ERR_NoError


5.9 _7200_DO _Channel

@ Description

This function is used to write data from digital output channels (bit). There are 32 digital output channels on the PCI-7200. When performs this function, the digital output port is written to the corresponding channel.

* channel means each bit of digital input ports.

@ Syntax

Visual C++( Windows 3.11, Win-95, and Win-NT) int W_7200_DO_Channel (U8 do_ch_no, Boolean do_data)

Visual Basic (Windows 3.11, Win-95, and Win-NT) int W_7200_DO_Channel ( ByVal do_ch_no as Byte, ByVal do_data as Boolean )As Integer

C/C++ ( DOS) int _7200_DI_Channel(U8 do_ch_no, Boolean do_data )

@ Argument :

do_ch_no : the DI channel number, the value has to be set from 0 to 31.
do_data : either 0 (OFF) or 1 (ON).

@ Return Code :

ERR_NoError
ERR_InvalidDOChannel


5.10 _7200_DI_DMA_Start

@ Description

The function will perform digital input N times with DMA data transfer by using the following four sampling modes :

1. pacer trigger ( internal timer trigger),
2. external rising edge I_IRQ,
3. external falling edge I_IRQ,
4. I_REQ & I_ACK handshaking.

It will takes place in the background which will not be stop until the Nth input data is transfered or your program execute _7200_DI_DMA_Stop() function to stop the process.

After executing this function, it is necessary to check the status of the operation by using the function _7200_DI_DMA_Status(). The PCI-7200 Bus mastering DMA is different from tradition PC style DMA. Its description is as follow :

Bus Mastering DMA mode of PCI-7200 :

PCI bus mastering offers the highest possible speed available on the PCI-7200. When the function _7200_DI_DMA_Start is executed, it will enable PCI bus master operation. This is conceptually similar to DMA (Direct Memory Access) transfers in a PC but is really PCI bus mastering. It does not use an 8237-style DMA controller in the host computer and therefore isn't blocked in 64K max. groups. PCI-7200 bus mastering works as follows:

1. To set up bus mastering, first do all normal PCI-7200 initialization necessary to control the board in status mode. This includes testing for the presence of the PCI BIOS, determining the base addresses, slot number, vendor and device ID's, I/O or memory, space allocation, etc. Please make sure your PCI-7200 is plug in a bus master slot, otherwise this function will not be workable.

2. Load the PCI controller with the count and 32-bit physical address of the start of previously allocated destination memory which will accept data. This count is the number of bytes (not longwords!) transferred during the bus master operation and can be a large number up to 64 million (2^26) bytes. Since the PCI-7200 transfers are always longwords, this is 16 million longwords (2^24).

3. After the input sampling is started, the input data is stored in the FIFO of PCI controller. Each bus mastering data transfer continually tests if any data in the FIFO and then blocks transfer, the system will continuously loop until the conditions are satisfied again but will not exit the block transfer cycle if the block count is not complete. If there is momentarily no input data, the PCI-7200 will relinquish the bus temporarily but returns immediately when more input data appear. This operation continues until the whole block is done.

4. This operation proceeds transparently until the PCI controller transfer byte count is reached. All normal PCI bus operation applies here such as a receiver which cannot accept the transfers, higher priority devices requesting the PCI bus, etc. Remember that only one PCI initiator can have bus mastering at any one time. However, review the PCI priority and "fairness" rules. Also study the effects of the Latency Timer. And be aware that the PCI priority strategy (round robin rotated, fixed priority, custom, etc.) is unique to your host PC and is explicitly not defined by the PCI standard. You must determine this priority scheme for your own PC (or replace it).

5. The interrupt request from the PCI controller can be optionally set up to indicate that this longword count is complete although this can also be determined by polling the PCI controller.

@ Syntax

Visual C++( Windows 3.11, Win-95, and Win-NT) int W_7200_DI_DMA_Start (U8 mode, U32 count, U32 *di_buffer, Boolean wait_trg, U8 trg_pol)

Visual Basic (Windows 3.11, Win-95, and Win-NT) int W_7200_ DI_ DMA_Start (ByVal mode as Byte, ByVal count as Long, di_buffer by Long, ByVal wait_trg as Boolean, ByVal trg_pol as Byte )As Integer

C/C++ ( DOS)
int _7200_DI_DMA_Start(U8 mode, U32 count, U32 *di_buffer, Boolean wait_trig, U8 trig_pol)

@ Argument :

mode: Digital Input trigger modes
DI_MODE0 : Internal timer pacer ( TIME 0)
DI_MODE1 : external signal I_REQ rising edge
DI_MODE2 : external signal I_REQ falling edge
DI_MODE3 : I_REQ & I_ACK handshaking

count : the number of digital input samples
di_buffer : the start address of the memory buffer to store the DI data

**This memory should be double-word alignment,

wait_trig : The waiting status of trigger
DI_NONWAITING : the input sampling will be
start immediately
DI_WAITING : the input samples waiting
rising or falling edge trigger to start DI

trig_pol : trigger polarity
DI_RISING : rising edge trigger
DI_FALLING : falling edge trigger

@ Return Code :
ERR_NoError, ERR_BoardNoInit
ERR_InvalidDIOMode, ERR_InvalidDIOCnt
ERR_NotDWordAlign, ERR_DMATransferNotAllowed



5.11 _7200_DI_DMA_Status

@ Description

Since the _7200_DI_DMA_Start function is executed in background, you can issue the function _7200_DI_DMA_Status to check its operation status.

@ Syntax

Visual C++( Windows 3.11, Win-95, and Win-NT) int W_7200_DI_ DMA_Status ( U8 *status, U32 * count)

Visual Basic (Windows 3.11, Win-95, and Win-NT) int W_7200_ AD_Status ( status as Byte, count as Long )As Integer

C/C++ ( DOS)
int _7200_AD_DMA_Status( U8 *status , U32 *count )

@ Argument :

status : status of the DMA data transfer 0 : DI_DMA_STOP : DMA is completed
1 : DI_DMA_RUN : DMA is not completed

count : the numbers of A/D data which has been transferred.

@ Return Code :

ERR_NoError


5.12 _7200_DI_DMA_Stop

@ Description

This function is used to stop the DMA data transferring. After executing this function, the _7200_DI_DMA_START function is stopped. The function returns the number of the data which has been transferred, no matter if the digital input DMA data transfer is stopped by this function or by the DMA terminal count ISR.

@ Syntax

Visual C++( Windows 3.11, Win-95, and Win-NT) int W_7200_AD_ DMA_Stop ( U32 * count)

Visual Basic (Windows 3.11, Win-95, and Win-NT) int W_7200_ AD_DMA_Stop ( count as Long )As Integer

C/C++ ( DOS) int _7200_AD_DMA_Stop( U32 *count )

@ Argument :

count : the number of DI data which has been transferred.

@ Return Code :

ERR_NoError
ERR_BoardNoInit


5.13 _7200_CheckHalfReady

@ Description

When you use _7200_DI_DMA_Start() to sample digital input data and _7200_DblBufferMode is set as enable. You must use _7200_CheckHalfReady() to check data ready or not in double buffer, size of data is half of doubleBuf (count/2) and using _7200_DblBufferTransfer() to get data.

@ Syntax

Visual C++( Windows 3.11, Win-95, and Win-NT) int W_7200_CheckHalfReady (Boolean * halfReady)

Visual Basic (Windows 3.11, Win-95, and Win-NT) int W_7200_CheckHalfReady (halfReady as Boolean)As Integer

C/C++ ( DOS)
int _7200_CheckHalfReady(Booelan *halfReady )

@ Argument :

halfReady : TRUE or FALSE.

@ Return Code :

ERR_NoError


5.14 _7200_DblBufferTransfer

@ Description

Using this function to move the input data to user buffer.

@ Syntax

Visual C++( Windows 3.11, Win-95, and Win-NT) int W_7200_ DblBufferTransfer (U32 *userBuffer)

Visual Basic (Windows 3.11, Win-95, and Win-NT)

int W_7200_ DblBufferTransfer (userBuffer as Long) As Integer

C/C++ ( DOS)
int _7200_DblBufferTransfer( U32 *userBuffer )

@ Argument :

userBuffer : user buffer for A/D converted data, size of user buffer is half of doubleBuf (count /2).

@ Return Code :

ERR_NoError
ERR_NotHalfReady


5.15 _7200_GetOverrunStatus

@ Description

When you use _7200_DI_DMA_Start() to convert A/D data and if you do not use _7200_DblBufferTransfer to move converted data then the double buffer overrun will occur, using this function to check overrun count.

@ Syntax

Visual C++( Windows 3.11, Win-95, and Win-NT) int W_7200_ GetOverrunStatus (U32 * overrunCount)

Visual Basic (Windows 3.11, Win-95, and Win-NT) int W_7200_ GetOverrunStatus (overrunCount as Long) As Integer

C/C++ ( DOS) int _7200_GetOverrunStatus(U32 *overrunCount )

@ Argument :

overrunCount: number of overrun counts.

@ Return Code :

ERR_NoError


5.16 _7200_DO_DMA_Start

@ Description

The function will perform digital output N times with DMA data transfer by using the following four sampling modes :

1. pacer trigger ( internal timer trigger, TIME 1 ),
2. Internal timer pacer with O_REQ enable
3. O_REQ & O_ACK handshaking.

It will takes place in the background which will not be stop until the Nth conversion has been completed or your program execute _7200_DO_DMA_Stop() function to stop the process. After executing this function, it is necessary to check the status of the operation by using the function _7200_DO_DMA_Status().

@ Syntax

Visual C++( Windows 3.11, Win-95, and Win-NT) int W_7200_DO_DMA_Start (U8 mode, U32 count, U32 *do_buffer, Boolean repeat)

Visual Basic (Windows 3.11, Win-95, and Win-NT) int W_7200_ DO_ DMA_Start (ByVal mode as Byte, ByVal count as Long, ad_buffer by Long, ByVal repeat as Boolean )As Integer

C/C++ ( DOS)
int _7200_DO_DMA_Start(U8 mode, U32 count, U32 *do_buffer, int wait_trig, int trig_pol)

@ Argument :
mode: Digital output trigger modes
DO_MODE_0 : Internal timer pacer ( TIME 1)
DO_MODE_1 : Internal timer pacer with O_REQ enable
DO_MODE_2 : O_REQ & I_REQ handshaking

count : the number of digital output data
do_buffer : the start address of the memory buffer to store the DI data.

This memory should be double-word alignment,

repeat : The digital output will be continuous or only one shot
CONTINUOUS : digital output will be continuous until the _7200_DO_DMA_STOP() is called.
ONE_SHOT : digital output only one-shot.

@ Return Code :
ERR_NoError
ERR_InvalidDIMode
ERR_InvalidBoardNumber
ERR_BoardNoInit
ERR_InvalidDIOCnt
ERR_NotDWordAlign
ERR_DMATransferNotAllowed



5.17 _7200_DO_DMA_Status

@ Description

Since the _7200_DO_DMA_Start function is executed in background, you can issue the function _7200_DO_DMA_Status to check its operation status.

@ Syntax

Visual C++( Windows 3.11, Win-95, and Win-NT) int W_7200_DO_ DMA_Status (U8 *status, U32 * count)

Visual Basic (Windows 3.11, Win-95, and Win-NT) int W_7200_ DO_Status ( status as Byte, count as Long )As Integer

C/C++ ( DOS)
int _7200_DO_DMA_Status( U8 *status , U32 *count )

@ Argument :

status : status of the DMA data transfer
0 : DO_DMA_STOP : DMA is completed
1 : DO_DMA_RUN : DMA is not completed

count : the numbers of A/D data which has been transferred.

@ Return Code :

ERR_NoError


5.18 _7200_DO_DMA_Stop

@ Description

This function is used to stop the DMA data transferring. After executing this function, the _7200_DO_DMA_START function is stopped. The function returns the number of the data which has been transferred, no matter if the digital input DMA data transfer is stopped by this function or by the DMA terminal count ISR.

@ Syntax

Visual C++( Windows 3.11, Win-95, and Win-NT) int W_7200_DO_ DMA_Stop ( U32 * count)

Visual Basic (Windows 3.11, Win-95, and Win-NT) int W_7200_ DO_DMA_Stop ( count as Long )As Integer

C/C++ ( DOS)
int _7200_DO_DMA_Stop( U32 *count )

@ Argument :

count : the numbers of digital output data which has been transferred.

@ Return Code :

ERR_NoError
ERR_BoardNoInit



5.19 _7200_DI_Timer

@ Description

This function is used to set the internal timer pacer for digital input. There are two configuration for the internal timer pacer :

1. Non-cascaded ( One COUNTER 0 only)

Timer pacer frequency = 4Mhz / C0

2. Cascaded (TIME2 cascaded with COUNTER0)

Timer pacer frequency = 4Mhz / (C0 * C2)

@ Syntax

Visual C++( Windows 3.11, Win-95, and Win-NT) int W_7200_DI_Timer ( U16 c0, U16 c2, Boolean mode)

Visual Basic (Windows 3.11, Win-95, and Win-NT) int W_7200_ DO_DMA_Stop ( ByVal c0 as Integer, ByVal c2 as Boolean )As Integer

C/C++ ( DOS)
int _7200_DO_DMA_Stop(U16 c0, U16 c2, Boolean mode)

@ Argument :

c0 : frequency divider of Counter #0
c2 : frequency divider of Counter #2

mode : TIMER_NONCASCADE or TIMER_CASCADE

@ Return Code :

ERR_NoError
ERR_InvalidBoardNumber
ERR_InvalidTimerMode
ERR_BoardNoInit


5.20 _7200_DO_Timer

@ Description

This function is used to set the internal timer pacer for digital output. There are two configuration for the internal timer pacer :

1. Non-cascaded ( One COUNTER 0 only)

Timer pacer frequency = 4Mhz / C1

2. Cascaded (TIME2 cascaded with COUNTER0)

Timer pacer frequency = 4Mhz / (C1 * C2)

@ Syntax

Visual C++( Windows 3.11, Win-95, and Win-NT) int W_7200_DO_Timer ( U16 c1, U16 c2, Booelan mode)

Visual Basic (Windows 3.11, Win-95, and Win-NT) int W_7200_ DO_DMA_Stop ( ByVal c1 as Integer, ByVal c2 as Boolean )As Integer

C/C++ ( DOS)
int _7200_DO_DMA_Stop(U16 c1, U16 c2, Boolean mode)

@ Argument :

c1 : frequency divider of Counter #1
c2 : frequency divider of Counter #2

mode : TIMER_NONCASCADE or TIMER_CASCADE

@ Return Code :

ERR_NoError
ERR_InvalidBoardNumber
ERR_InvalidTimerMode
ERR_BoardNoInit



Appendix. 8254 Programmable Interval Timer

Note : The material of this section is adopted from "Intel Microprocessor and Peripheral Handbook Vol. II Peripheral"

A.1 The Intel (NEC) 8254

The Intel(NEC) 8254 contains three independent, programmable, multi-mode 16 bit counter/timers. The three independent 16 bit counters can be clocked at rates from DC to 5 MHz. Each counter can be individually programmed with 6 different operating modes by appropriately formatted control words. The most commonly uses for the 8254 in microprocessor based system are:

• programmable baud rate generator
• event counter
• binary rate multiplier
• real-time clock
• digital one-shot
• motor control

For more information about the 8254 , please refer to the NEC Microprocessors and peripherals or Intel Microprocessor and Peripheral Handbook.

A.2 The Control Byte

The 8254 occupies 8 I/O address locations in the PCI-7200 I/O map. As shown below.

Before loading or reading any of these individual counters, the control byte ( Base + C ) must be loaded first. The format of control byte is :

Control Byte : (Base + 7, Base + 11)

· SC1 & SC1 - Select Counter ( Bit7 & Bit 6)

· RL1 & RL0 - Select Read/Load operation ( Bit 5 & Bit 4)

· M2, M1 & M0 - Select Operating Mode ( Bit 3, Bit 2, & Bit 1)

· BCD - Select Binary/BCD Counting ( Bit 0)

NOTES:

1. The count of the binary counter is from 0 up to 65,535.
2. The count of the BCD counter is from 0 up to 99,999.

A.3 Mode definition

In 8254, there are six different operating modes can be selected. The they are :

· Mode 0 : interrupt on terminal count
The output will be initially low after the mode set operation. After the count is loaded into the selected count register, the output will remain low and the counter will count. When terminal count is reached, the output will go high and remain high until the selected count register is reloaded with the mode or a new count is loaded. The counter continues to decrement after terminal count has been reached.

Rewriting a counter register during counting results in the following:

(1) Write 1st byte stops the current counting.
(2) Write 2nd byte starts the new count.

· Mode 1 : Programmable One-Shot.
The output will go low on the count following the rising edge of the gate input. The output will go high on the terminal count. If a new count value is loaded while the output is low it will not affect the duration of the one-shot pulse until the succeeding trigger. The current count can be read at anytime without affecting the one-shot pulse.

The one-shot is re-triggerable, hence the output will remain low for the full count after any rising edge of the gate input.

· Mode 2 : Rate Generator.
divide by N counter. The output will be low for one period of the input clock. The period from one output pulse to the next equals the number of input counts in the count register. If the count register is reloaded between output pulses the present period will not be affected, but the subsequent period will reflect the new value.

The gate input when low, will force the output high. When the gate input goes high, the counter will start form the initial count. Thus, the gate input can be used to synchronized by software.

When this mode is set, the output will remain high until after the count register is loaded. The output then can also be synchronized by software.

· Mode 3 : Square Wave Rate Generator.
Similar to MODE 2 except that the output will remain high until one half the count has been completed (or even numbers) and go low for the other half of the count. This is accomplished by decrement the counter by two on the falling edge of each clock pulse. When the counter reaches terminal count, the state of the output is changed and the counter is reloaded with the full count and the whole process is repeated.

if the count is odd and the output is high, the first clock pulse (after the count is loaded) decrements the count by 1. Subsequent clock pulses decrement the clock by 2 After time-out, the output goes low and the full count is reloaded. the first clock pulse (following the reload) decrements the counter by 3. Subsequent clock pulses decrement the count by 2 until time-out. Then the whole process is repeated. In this way, if the count is odd, the output will be high for (N + 1)/2 counts and low for (N - 1)/2 counts.

In Modes 2 and 3, if a CLK source other then the system clock is used, GATE should be pulsed immediately following Way Rate of a new count value.

· Mode 4 : Software Triggered Strobe.
After the mode is set, the output will be high. When the count is loaded, the counter will begin counting. On terminal count, the output will go low for one input clock period, then will go high again.

If the count register is reloaded during counting, the new count will be loaded on the next CLK pulse. The count will be inhibited while the GATE input is low.

· Mode 5 : Hardware Triggered Strobe.

The counter will start counting after the rising edge of the trigger input and will go low for one clock period when the terminal count is reached. The counter is re-triggerable. the output will not go low until the full count after the rising edge of any trigger.

The detailed description of the mode of 8254, please refer the Intel Microsystem Components Handbook.



Product Warranty/Service

Seller warrants that equipment furnished will be free form defects in material and workmanship for a period of one year from the confirmed date of purchase of the original buyer and that upon written notice of any such defect, Seller will, at its option, repair or replace the defective item under the terms of this warranty, subject to the provisions and specific exclusions listed herein.

This warranty shall not apply to equipment that has been previously repaired or altered outside our plant in any way as to, in the judgment of the manufacturer, affect its reliability. Nor will it apply if the equipment has been used in a manner exceeding its specifications or if the serial number has been removed.

Seller does not assume any liability for consequential damages as a result from our products uses, and in any event our liability shall not exceed the original selling price of the equipment.

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The equipment must be returned postage-prepaid. Package it securely and insure it. You will be charged for parts and labor if you lack proof of date of purchase, or if the warranty period is expired.

©1995 Circuit Specialists, Inc.