@Copyright 1997

 

All Rights Reserved.

 

Manual edition 1, April 1997

 

The information in this document is subject to change without prior notice in order to improve reliability, design and function and does not represent a commitment on the part of the manufacturer.

 

In no event will the manufacturer be liable for direct, indirect, special, incidental, or consequential damages arising out of the use or inability to use the product or documentation, even if advised of the possibility of such damages.

 

This document contains proprietary information protected by copyright. All rights are reserved. No part of this manual may be reproduced by any mechanical, electronic, or other means in any form without prior written permission of the manufacturer.


 

Trademarks

 

PCI-7248 and PCI-7296 are registered trademarks of ADLink Technology Inc. Other product names mentioned herein are used for identification purposes only and may be trademarks and/or registered trademarks of their respective companies.


 



HOW TO USE THIS GUIDE
INTRODUCTION
1.1 Features
1.1.1 Digital I/O Ports
1.1.2 Timer / Counter and Interrupt System
1.1.3 Miscllenous
1.2 Applications
1.3 Specifications
INSTALLATION
2.1 What You Have
2.2 Unpacking
2.3 PCI-7248 Layout
2.4 PCI-7296 Layout
2.5 Connector Pin Assignment
2.6 Jumper Description
2.6.1 Power on State of Ports
2.6.2 12V Power Supply Configuration
2.7 PCI-7248/7296 Installation Outline
2.7.1 Hardware configuration
2.7.2 PCI slot selection
2.7.3 Installation Procedures
2.7.4 Running the 7248UTIL.EXE or 7296UTIL.EXE
OPERATION THEOREM
3.1 Digital I/O Ports
3.1.1 Introduction
3.1.2 8255 Mode 0
3.1.3 Special Funtion of the DIO Signals
3.1.4 Digital I/O Port Programming
3.1.5 Control Word
3.1.6 Power On Configuration
3.1.7 Note for Output Data
3.2 8254 Timer / Counter Operation
3.2.1 Introduction
3.2.2 Cascaded 32 bits Timer
3.2.3 Event Counter and Edge Control
3.3 Interrupt System
3.3.1 System Architecture
3.3.2 IRQ Level Setting
3.3.3 Dual Interrupt System
3.3.4 Interrupt Source Contorl
3.3.5 Self Interrupt Trigger
3.4 12V and 5V Power Supply
C/C++ SOFTWARE LIBRARIES
4.1 Installation

4.1.1 Backup Your Disk 25
4.1.2 Installation 25
4.2 Running Testing Utility( 7296UTIL.EXE) 26
4.3 Software Driver Naming Convention 26
4.4 _7248/96_Initial 27
4.5 _7248/96_DI 28
4.6 _7248/96_DO 30
4.7 _7248/96_Config_Port 32
4.8 Reset PCI-7248/96 cards 34
PRODUCT WARRANTY/SERVICE 35

 

How to Use This Guide


 

This manual is designed to help you use the PCI-7248/96. It describes how to modify and control various functions on the PCI-7248/96 card to meet your requirements. It is divided into three chapters:

· Chapter 1, "Introduction," gives an overview of the product 9273 features. applications, and specifications.

1

 

Introduction


 

The PCI-7248 and PCI-7296 are multi-functions digital I/O board used for industrial PC with PCI bus. The PCI cards are plug and play therefore it is not nessary to set any jumper for matching the PC environment. PCI-7248 is a 48-bit Parallel DIO card and PCI-7296 is an 96-bit parallel DIO card.

 

The PCI-7248 emulates two industry standard mode zero configuration of 8255 Programmable Peripheral Interface (PPI) chips. The PCI-7296 emulates four PPI chips. These two cards are compatible not only on hardware connectors but also on software programming. This manual is used to lead users to know how to operate these two cards.

 

Every PPI connector offers 3 ports: PA, PB, and PC. The PC can also be subdivided into 2 nibble-wide ( 4-bit) ports - PC Upper and PC Low. Two and four 50-pin male ribbon connectors come equipped with the PCI-7248 and PCI-7296. Each connector is corresponding to one PPI chip with 24 DIO points.

 

The PCI-7248/96 is programmed using the ADLink`s software library. The programming of these PCI cards is as easy as AT bus add-on cards.


1.1 Features

 

1.1.1 Digital I/O Ports

 

1.1.2 Timer / Counter and Interrupt System

 

1.1.3 Miscllenous


1.2 Applications

1.3 Specifications


BORDER=1 CELLSPACING=1> I/O channels 48-bit for PCI-7248
96-bit for PCI-7296 Input Signal Logic High Voltage :2.0 V to 5.25V
Logic Low Voltage : 0.0 V to 0.80V
Logic High Current : 20.0 uA
Logic Low Current : -0.2 mA Output Signal Logic High Voltage : Minimum 2.4 V
Logic Low Voltage : Maximum 0.5V
Logic High Current : -15.0 mA
Logic Low Current : 24.0 mA Operating Temperature 0 ~ 60 C Storage Temperature -20 ~ 80 C Humidity 5% ~ 95% non-condensing I/O Connectors 50-pin male ribbon cable connector Bus PCI bus IRQ Level Set by Plug and Play BIOS I/O port address Set by Plug and Play BIOS Power Consumption
(without external devices)
PCI-7248 :

450mA @5VDC ( Typical)

540mA @5VDC ( Maximum)

PCI-7296 :

600mA @5VDC ( Typical)

750mA @5VDC ( Maximum) Transfer Rate 500 K bytes/sec (Typical)
Size PCI-7248 : 147mm x 98.8mm
PCI-7296 : 165mm x 98.8 mm

 

2

 

Installation


This chapter describes how to install the PCI-7248 or PCI-7296. At first, the contents in the package and unpacking information that you should be careful are described.


2.1 What You Have


If any of thes e items is missing or damaged, contact the dealer from whom you purchased the product. Save the shipping materials and carton in case you want to ship or store the product in the future.


2.2 Unpacking

2.3 PCI-7248 Layout


2.4 PCI-7296 Layout





Figure 2.4 PCI-7296 Layout


2.5 Connector Pin Assignment

The I/O ports of PCI-7248/96 emulate the mode 0 configuration of the 8255 general purpose programmable peripheral interface. This card comes equipped with two/four 50-pin male IDC connectors that interface with OPTO-22. Figure 2.5 shows the circuits and pin assignment of PCL-7248/96's connectors (CN1~CN4) .

Note : The pin assignment of the CN1 ~ CN4 connectors are identical.






 

 

 

 

 

 

 

2.6 Jumper Description

 

The PCI-7248/96 DIO cards are `plug and play' cards using PCI bus. It is not necessary to setup the card configurations to fit the computer system`s hardware configurations. However, to fit users' versitile operation environment, there are still a few jumpers to set the power on state of ports and the usage of the +12V output pins.

 

2.6.1 Power on State of Ports

 

For every port on the PCI-7248/96 cards, the power on state is set as input, therefore, the voltage could be pulled high, pulled low, or floating. It is dependent on the jumpers setting. Table 2.6 lists the reference number of the jumpers and the corresponding port names.


Jumper

Port Name

Remarks

JA1

P1A (Port A of CN1) for both PCI-7248/7296

JB1

P1B (Port B of CN1) for both PCI-7248/7296

JC1

P1C (Port C of CN1) for both PCI-7248/7296

JA2

P2A (Port A of CN2) for both PCI-7248/7296

JB2

P2B (Port B of CN2) for both PCI-7248/7296

JC2

P2C (Port C of CN2) for both PCI-7248/7296

JA3

P3A (Port A of CN3) for PCI-7296 only

JB3

P3B (Port B of CN3) for PCI-7296 only

J C3

P3C (Port C of CN3) for PCI-7296 only

JA4

P4A (Port A of CN4) for PCI-7296 only

JB4

P4B (Port B of CN4) for PCI-7296 only

J C4

P4C (Port C of CN4) for PCI-7296 only

Table 2.6 Jumpers and Port names list

 

The physical meaning of all the jumpers are identical. The power on state of each port can be set independently. The defalut is to pull all signals high. The following diagram use JA1 as an example to show the possible configurations.

 

 

2.6.2 12V Power Supply Configuration

 

The pin 2 and pin 4 of the CN1 ~ CN4 50-pin OPTO-22 connectors can be configured as 12V power supply or ground. Please refer to Figure 2.5 for the 12 volts power supply circuits. JP1~JP4 set the 12V power of CN1~CN4 respectively. The default configuration is short to ground. The following diagram shows the setting of JP2, shorting the pin 2 and pin 4 of CN2 to ground.

 


2.7 PCI-7248/7296 Installation Outline

 

2.7.1 Hardware configuration :

PCI-7248/7296 has plug and play component, the card can requests an interrupt via a system call. The system BIOS responds with an interrupt assignment based on the PCI-7248/7296`s configuration registers and on known system parameters( which are set by system BIOS). Interrupts assigned are a function of the system, the system BIOS, the installed driver and the installed PCI boards.

Memory usage ( I/O port locations) of the PCI-7248/7296 is also assigned by system BIOS. The address assignment is done on a board-by-board basis for all PCI-7248s in the system.

 

2.7.2 PCI slot selection

 

Your computer will probably have both PCI and ISA slots. Do not force the PCI-7248 into a PC/AT slot.


2.7.3 Installation Procedures

 

2.7.4 Running the 7248UTIL.EXE or 7296UTIL.EXE

 

 

3

 

Operation Theorem


 

In this chapter, the operation theorem of the digital I/O, timer, interrupt are introduced. Before programming or applying the PCI-7248/96 cards to your applications, please go through this chapter to understand the features of the functions.


3.1 Digital I/O Ports

 

3.1.1 Introduction

The PCI-7248 / PCI-7296 can emulate two / four mode 0 configuration of 8255 programmable peripheral interface (PPI) chips. There are 24 DIO signals for every PPI. The PCI-7248 and PCI-7296 has 48 and 96 DIO signals respectively.

 

3.1.2 8255 Mode 0

 


3.1.3 Special Funtion of the DIO Signals

Two I/O signals (PC0 and PC3) of CN1 and CN2 can be used to generate hardware interrupt. Refer to the `interrupt system' section for details about the interrupt control. In addition, the P1C4 signals can be used as input signal of event counter.

 

3.1.4 Digital I/O Port Programming COLOR="#000000">

Users can write the digital output value to or read back the digital signal level from the PPI ports by using the software library. Here we define the port name in Table 3.1.1. These port names are used both in software library and all through this manual. Althought there are four 8255 PPIs in PCI-7296 and only two 8255 PPIs in PCI-7248, the programming for PCI-7248 and PCI-7296 are compatible.

Connector


numbers

CN1

CN2

CN3

CN4

P1A

P2A

P3A

P4A

Port

P1B

P2B

P3B

P4B

Names

P1C

P2C

P3C

P4C

P1CTRL

P2CTRL

P3CTRL

P4CTRL

Table 3.1.1 I/O Port Names


There are four ports on every 8255 PPI, including port A,B,C and the control prot. PA,PB and PC could be wrote or read but the control port is write only. Refer to section 4.3 for details about programming of DIO ports.

 

3.1.5 Control Word

The control word written in the control port is used to setup PA, PB and PC as input or output port. Fig 3.1 shows the format of the control word. Table 3.1.2 shows the 16 possible control word and the respective I/O configurations .


 

Control


Word

D4 D3 D1 D0

PORTA

PORT C


UPPER

PORT B

PORT C LOWER

00H

0 0 0 0

O/P

O/P

O/P

O/P

01H

0 0 0 1

O/P

O/P

O/P

I/P

02H

0 0 1 0

O/P

O/P

I/P

O/P

03H

0 0 1 1

O/P

O/P

I/P

I/P

08H

0 1 0 0

O/P

I/P

O/P

O/P

09H

0 1 0 1

O/P

I/P

O/P

I/P

0AH

0 1 1 0

O/P

I/P

I/P

O/P

0BH

0 1 1 1

O/P

I/P

I/P

I/P

10H

1 0 0 0

I/P

O/P

O/P

O/P

11H

1 0 0 1

I/P

O/P

O/P

I/P

12H

1 0 1 0

I/P

O/P

I/P

O/P

13H

1 0 1 1

I/P

O/P

I/P

I/P

18H

1 1 0 0

I/P

I/P

O/P

O/P

19H

1 1 0 1

I/P

I/P

O/P

I/P

1AH

1 1 1 0

I/P

I/P

I/P

O/P

1BH*

1 1 1 1

I/P

I/P

I/P

I/P

Table 3.1.2 Summary of control word (D0 - D4).

 

 


3.1.6 Power On Configuration

The defalut configuration after power on, hardware reset or software reset is to set all ports as input ports, therefore the users won`t worry about damaging the external devices when system is power on. In addition, the default signal level can be pulled high or pulled low by setting the jumpers. Refer to section 2.6 for setting the power on state of the DIO ports.

 

3.1.7 Note for Output Data

Be careful about the initial condition of dgital output signals. If user set the control word as output port after power on, the previous uncertain output value will be put on the output pins immediately. Therefore, BE SURING TO SET A SAFE OUTPUT VALUE BEFORE SETTING ANY PORT AS OUT PORT.


3.2 8254 Timer / Counter Operation

 

3.2.1 Introduction

One 8254 programmable timer/counter chip is installed in PCI-7248/7296. There are three counters in one 8254 chip and 6 possible operation modes for each counter. The block diagram of the timer /counter system is shown in Figure 3.2.



The timer #1 and timer #2 of the 8254 chip are cascaded as a 32-bits programmable timer. In software library, the timer #1 and #2 are always set as mode 2 (rate generater).

In software library, the counter #0 is used as an event counter, that is, interrupt on terminal count of 8254 mode 0 . Please refer to section 4.4 for programming the timer / counter functions.

 

3.2.2 Cascaded 32 bits Timer

The input clock frequence of the cascaded timers is 2M Hz. The output of the timer is send to the interrupt system (refer to section 3.3). Therefore, the maximum and minimum watchdog timer interrupt frequency is (2M Hz)/(2*2)=(500K Hz) and (2M Hz)/(65535*65535) respectively.

 

 

3.2.3 Event Counter and Edge Control

The counter #0 of the 8254 chip can be used as event counter. The input of counter #0 is PC4 of CN1 (P1C4). The counter clock trigger direction (H to L or Lto H) is programmable. The gate control is always enable. The output is send to interrupt system which named as event IRQ. If counter #0 is set as 8254 mode 0, the event counter IRQ will generate when the counter value is counting down to zero.



 

3.3 Interrupt System

 

3.3.1 System Architecture

The PCL-7248/96`s interrupt system is a powerful and flexable system which is suitable for many applications. The system is a Dual Interrupt System. The dual interrupt means the hardware can generate two interrupt request signals in the same time and the software can service these two request signals by ISR. Note that the dual interrupt do not mean the card occupy two IRQ levels.


The two interrupt request signals (INT1 and INT2) are comes from digital input signals or the timer / counter output. An interrupt sources multiplexer (MUX) is used to select the IRQ sources. Fig 3.3.1 shows the interrupt system.

Fig 3.3.1 Dual Interrupt System of PCI-7248/96


3.3.2 IRQ Level Setting

There is only one IRQ level is used by this card, althought it is a dual interrupt system. This card uses INT #A interrupt request siganl to PCI bus. The mother board circuits will transfer INT #A to one of the AT bus IRQ levels. The IRQ level is set by the PCI plug and play BIOS and saved in the PCI controller. It is not necessary for users to set the IRQ level. Users can get the IRQ level setting by software library. Refer the section 4.5.

3.3.3 Dual Interrupt System

The PCI controller of PCI-7248/96 can receive two hardware IRQ sources. However, a PCI controller can generate only one IRQ to PCI bus, the two IRQ sources must be distinguished by ISR of the application software if the two IRQ are all used.

The application software can use the "get_PCI72_irq_status" function to distinguishe which interrupt is inserted. After servicing an IRQ signal, users must check if another IRQ is also assserted, then clear current IRQ to allow the next IRQ coming in.

The two IRQs are named as INT1 and INT2. INT1 comes from P1C0, P1C3 or the event counter interrupt. INT2 comes from P2C0, P2C3 or the timer interrupt. The sources of INT1 and INT2 is selectable by the Interrupt Source Control (ISC) Register.


3.3.4 Interrupt Source Contorl

There are four bits to control the IRQ sources of INT1 and INT2. The Table 3.3.1 shows the selection of the IRQ sources and the interrupt trigger conditions.


If the application need only one IRQ, you can disable one of the IRQ sources by software. If your application do not need any IRQ source, you can disable all the two interrupts. However, the PCI BIOS still assign a IRQ level to the PCI card and occupy the PC resource, if you only disable the IRQ sources without change the initial condition of the PCI controller.


It is not suggested to re-design the initial condition of the PCI card by users` own application software. If users want to disable the IRQ level, user can use the ADLink's utility `INIT7296.EXE' to chage power on interrupt setting.

INT1

D3

D2

D1

D0

IRQ Sources IRQ Trigger Condition

disable

X

X

0

0

INT1 disable --

mode 1

X

X

0

1

~P1C0 falling edge of P1C0

mode 2

X

X

1

0

P1C0 OR ~P1C3 (see following)

mode 3

X

X

1

1

Event Counter Counter count down to 0

INT2

D3

D2

D1

D0

IRQ Sources IRQ Trigger Condition

disable

0

0

X

X

INT2 disable --

mode 1

0

1

X

X

~P2C0 falling edge of P2C0

mode 2

1

0

X

X

P2C0 OR ~P2C3 (see following)

mode 3

1

1

X

X

Timer Output Timer count down to 0

Table 3.3.1 ISC register format


When the IRQ sources is set as "P1C0 OR ~P1C3", the IRQ trigger conditions are summarized in table 3.3.2,

P1/2C0

P1/2C3

IRQ Trigger Condition

High

X

PC0=`H' disable all IRQ

X

Low

PC3=`L' disable all IRQ

Low

1->0

PC3 falling edge trigger when PC0=L

0->1

High

PC0 rising edge trigger when PC3=H

Because the P1/P2C0 and P1/P2C3 are external signals, the applications can utilize the combination of the four signals to generate a proper IRQ.

 

3.3.5 Self Interrupt Trigger

Although the PCL-7248/96's interrupt signals are normal received from external peripherals. It can also generate a test output signal to emulate an interrupt from an external device. An example program is shown in the diskette for reference.


3.4 12V and 5V Power Supply

The OPTO-22 compatible connectors provide external devices the +12 volts and +5 volts power supply. To aviod short or overload of the power supply, the resetable fuses are added on all the power supply signals. Refer to Figure 2.5.

The maximun current for 5 volts on every connector is 0.5 A. If the load current is larger than 0.5 A, the resistance of ..... fuse will increase because of the temperature rising. The rising resistance will cause the power supply drop and reduce current. If the overload or short condition is removed, the fuse will get to normal condition. It is not nessary to repair or re-install the fuse.

The maximum current of 12 volts for all the four connectors is also 0.5 A. The action of the fuse is the same as which used for +5V power. The limitation is more resitrict than 5V power supply because the PCI bus can not provide large current.

 

C/C++ Software Libraries


 

In this chapter, the PCI-7248 and PCI-7296 software library, C/C++ language library, for DOS is described.

4.1 Installation

 

4.1.1 Backup Your Disk

The Utility Software and Library of PCI-7248/7296 are under DOS environment. The drivers are compatible with DOS 3.0 or higher versions. It is advisable to make a back up copy before using the software.

4.1.2 Installation

A:\DOS> SETUP


4.2 Running Testing Utility( 7296UTIL.EXE )

 

 

4.3 Software Driver Naming Convention

The functions of PCI-7248's or PCI-7296's software drivers are using full-names to represent the functions' real meaning. The naming convention rules are :

 


4.4 _7248/96_Initial

(for PCI-7248)
U16 _7248_Initial(U16 *existCards, PCI_INFO *pciInfo )
(for PCI-7248)
U16 _7296_Initial(U16 *existCards, PCI_INFO *pciInfo )

existCards : The numbers of installed PCI-7248/7296 cards. The returned value shows how many PCI-7248/7296 cards are installed in your system.

pciinfo: It is a structure to memorize the PCI bus plug and play initiallization information which is decided by p&p BIOS. The PCI_INFO structure is defined in PCI_7248.H or PCI_7296.H. The base I/O address and the interrupt channel number is stored in pciinfo which is for reference.

 

ERR_NoError
ERR_PCIBiosNotExist

 

4.5 _7248/96_DI

D7

D6

D5

D4

D3

D2

D1

D0

PA7

PA6

PA5

PA4

PA3

PA2

PA1

PA0

PB7

PB6

PB5

PB4

PB3

PB2

PB1

PB0

PC7

PC6

PC5

PC4

PC3

PC2

PC1

PC0


(for PCI-7248)
U16 _7248_DI( U16 cardNo, U16 channelPort, U16 *diData )
(for PCI-7296)
U16 _7296_DI( U16 cardNo, U16 channelPort, U16 *diData )


cardNo : card number to select borad

channelPort : port of each channel
PCI_CH0_PA : CH1's Port A
PCI_CH0_PB : CH1's Port B
PCI_CH0_PC : CH1's Port C
PCI_CH0_PCU : CH1's Port C Upper Nibble
PCI_CH0_PCL : CH1's Port C Low Nibble
PCI_CH1_PA : CH2's Port A
PCI_CH1_PB : CH2's Port B
PCI_CH1_PC : CH2's Port C
PCI_CH1_PCU : CH2's Port C Upper Nibble
PCI_CH1_PCL : CH2's Port C Low Nibble
PCI_CH2_PA : CH2's Port A
PCI_CH2_PB : CH2's Port B
PCI_CH2_PC : CH2's Port C
PCI_CH2_PCU : CH2's Port C Upper Nibble
PCI_CH2_PCL : CH2's Port C Low Nibble
PCI_CH3_PA : CH3's Port A
PCI_CH3_PB : CH3's Port B
PCI_CH3_PC : CH3's Port C
PCI_CH3_PCU : CH3's Port C Upper Nibble
PCI_CH3_PCL : CH3's Port C Low Nibble

Note : CH2 and CH3 are only available for PCI-7296 card only.

diData :
return 8-bit value from digital port.

 

ERR_NoError

 


4.6 _7248/96_DO

(for PCI-7248)
U16 _7248_DO(U16 cardNo, U16 channelPort, U8 do_data )
(for PCI-7296)
U16 _7296_DO(U16 cardNo, U16 channelPort, U8 do_data )

cardNo : card number to select borad channelPort :
channelPort : port of each channel
PCI_CH0_PA : CH1's Port A
PCI_CH0_PB : CH1's Port B
PCI_CH0_PC : CH1's Port C
PCI_CH0_PCU : CH1's Port C Upper Nibble
PCI_CH0_PCL : CH1's Port C Low Nibble
PCI_CH1_PA : CH2's Port A
PCI_CH1_PB : CH2's Port B
PCI_CH1_PC : CH2's Port C
PCI_CH1_PCU : CH2's Port C Upper Nibble
PCI_CH1_PCL : CH2's Port C Low Nibble
PCI_CH2_PA : CH2's Port A
PCI_CH2_PB : CH2's Port B
PCI_CH2_PC : CH2's Port C
PCI_CH2_PCU : CH2's Port C Upper Nibble
PCI_CH2_PCL : CH2's Port C Low Nibble
PCI_CH3_PA : CH3's Port A
PCI_CH3_PB : CH3's Port B
PCI_CH3_PC : CH3's Port C
PCI_CH3_PCU : CH3's Port C Upper Nibble
PCI_CH3_PCL : CH3's Port C Low Nibble

Note : CH2 and CH3 are only available for PCI-7296 card only.

do_data :
value will be written to digital output port


ERR_NoError

4.7 _7248/96_Config_Port

( For PCI-7248)
U16 _7248_Config_Port(U16 cardNo, U16 channelPort,
U16 direction )

( For PCI-7296)
U16 _7248_Config_Port(U16 cardNo, U16 channelPort,
U16 direction )

cardNo : card number to select borad channelPort :
channelPort : port of each channel
PCI_CH0_PA : CH1's Port A
PCI_CH0_PB : CH1's Port B
PCI_CH0_PC : CH1's Port C
PCI_CH0_PCU : CH1's Port C Upper Nibble
PCI_CH0_PCL : CH1's Port C Low Nibble
PCI_CH1_PA : CH2's Port A
PCI_CH1_PB : CH2's Port B
PCI_CH1_PC : CH2's Port C
PCI_CH1_PCU : CH2's Port C Upper Nibble
PCI_CH1_PCL : CH2's Port C Low Nibble
PCI_CH2_PA : CH2's Port A
PCI_CH2_PB : CH2's Port B
PCI_CH2_PC : CH2's Port C
PCI_CH2_PCU : CH2's Port C Upper Nibble
PCI_CH2_PCL : CH2's Port C Low Nibble
PCI_CH3_PA : CH3's Port A
PCI_CH3_PB : CH3's Port B
PCI_CH3_PC : CH3's Port C
PCI_CH3_PCU : CH3's Port C Upper Nibble
PCI_CH3_PCL : CH3's Port C Low Nibble

Note : CH2 and CH3 are only available for PCI-7296 card only.


direction :
port I/O direction
INPUT_PORT : the port is configure as INPUT
OUTPUT_PORT : the port is configure as OUTUT

ERR_NoError

 

 

4.8 Reset PCI-7248/96 cards

void _7248_Software_Reset( U16 cardNo)

void _7296_Software_Reset( U16 cardNo)

 

PRODUCT WARRANTY/SERVICE



SELLER WARRANTS THAT EQUIPMENT FURNISHED WILL BE FREE FORM DEFECTS IN MATERIAL AND WORKMANSHIP FOR A PERIOD OF ONE YEAR FROM THE CONFIRMED DATE OF PURCHASE OF THE ORIGINAL BUYER AND THAT UPON WRITTEN NOTICE OF ANY SUCH DEFECT, SELLER WILL, AT ITS OPTION, REPAIR OR REPLACE THE DEFECTIVE ITEM UNDER THE TERMS OF THIS WARRANTY, SUBJECT TO THE PROVISIONS AND SPECIFIC EXCLUSIONS LISTED HEREIN.

 

THIS WARRANTY SHALL NOT APPLY TO EQUIPMENT THAT HAS BEEN PREVIOUSLY REPAIRED OR ALTERED OUTSIDE OUR PLANT IN ANY WAY AS TO, IN THE JUDGMENT OF THE MANUFACTURER, AFFECT ITS RELIABILITY. NOR WILL IT APPLY IF THE EQUIPMENT HAS BEEN USED IN A MANNER EXCEEDING ITS SPECIFICATIONS OR IF THE SERIAL NUMBER HAS BEEN REMOVED.

 

SELLER DOES NOT ASSUME ANY LIABILITY FOR CONSEQUENTIAL DAMAGES AS A RESULT FROM OUR PRODUCTS USES, AND IN ANY EVENT OUR LIABILITY SHALL NOT EXCEED THE ORIGINAL SELLING PRICE OF THE EQUIPMENT.

 

THE EQUIPMENT WARRANTY SHALL CONSTITUTE THE SOLE AND EXCLUSIVE REMEDY OF ANY BUYER OF SELLER 9273 EQUIPMENT AND THE SOLE AND EXCLUSIVE LIABILITY OF THE SELLER, ITS SUCCESSORS OR ASSIGNS, IN CONNECTION WITH EQUIPMENT PURCHASED AND IN LIEU OF ALL OTHER WARRANTIES EXPRESSED IMPLIED OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, ANY IMPLIED WARRANTY OF MERCHANT ABILITY OR FITNESS AND ALL OTHER OBLIGATIONS OR LIABILITIES OF SELLER, ITS SUCCESSORS OR ASSIGNS.

 

THE EQUIPMENT MUST BE RETURNED POSTAGE-PREPAID. PACKAGE IT SECURELY AND INSURE IT. YOU WILL BE CHARGED FOR PARTS AND LABOR IF YOU LACK PROOF OF DATE OF PURCHASE, OR IF THE WARRANTY PERIOD IS EXPIRED.



©1995 Circuit Specialists, Inc.