Note : DO NOT APPLY POWER TO THE CARD IF IT HAS BEEN DAMAGED.

The only one jumper (JP1) on the PCI-9111 card is used to set the range of the analog output channel. The analog output range could be unipolar (0~10V) or bi-polar (-10V~+10V). The default setting is bi-polar.

The board configuration is done on a board-by-board basis for all PCI cards on your system. Because the configuration is controlled by the system BIOS and software, there is no jumpers for setting system parameters like base-address, and interrupt level.

The configuration is subject to change with every boot of the system when new boards are added or boards are removed.

If your system will not boot or if you experience erratic operation with your PCI board in place, it’s likely caused by an interrupt conflict (perhaps because you incorrectly described the ISA setup). In general, the solution, once you determine it is not a simple oversight, is to consult the BIOS documents that come with your system.

This chapter describes the connector of the PCI-9111, and the signal connection between the PCI-9111 and external devices, such as daughter boards or other devices.

The PCI-9111 comes equipped with two 20-pin insulation displacement connectors - CN1 and CN2 and one 37-pin D-type connector - CN3. The CN1 and CN2 are located on board and CN3 located at the rear plate.

CN1 is used for digital signal input, CN2 for digital signal output, CN3 for analog input, analog output, extended digital I/O and timer/counter's signals. The pin assignment for each connector is illustrated in the Figure 3.1 ~ Figure 3.3.

A.GND : Analog Signal Ground

D.GND : Digital Signal Ground

The PCI-9111 provides 16 single-ended analog input channels. The analog signal can be converted to digital value by the A/D converter. To avoid ground loops and get more accurate measurement of A/D value, it is quite important to understand the signal source type. The single-ended mode has only one input relative to ground and is suitable for connecting with the floating signal source. The floating source means it does not have any connection to real ground. Figure 3.4 shows the single-ended connection. Note that when more than two floating sources are connected, the sources must be with common ground.

The PCI-9111 has one analog output channel. The signal range can be uni-polar or bi-polar which are set by JP1.

The PCI-9111 provides 16 digital input and 16 digital output channels through the connector CN1 and CN2 on board. The digital I/O signal is fully TTL/DTL compatible. The detailed digital I/O signal specification can be referred to section 1.3.

The PCI-9111 can be connected with five different daughter boards, ACLD-8125, ACLD-9137, 9138, 9182, 9185, and 9188. The functionality and connections are specified as follows.

The ACLD-8125 has a 37-pin D-sub connector, which can connect with PCI-9111 through 37-pin assemble cable. The most outstanding feature of this daughter board is a CJC (cold junction compensation) circuit on board. You can directly connect the thermocouple on the ACL-8125 board. The CJC only suitable for High Gain version board.

The ACLD-9137 is a direct connector for the card which is equipped with 37-pin D-sub connector. This board provides a simple way for connection. It is very suitable for the simple applications that do not need complex signal condition before the A/D conversion is performed.

The ACLD-9182 is a 16 channel isolated digital input board. This board is connected with CN1 of PCI-9111 via 20-pin flat cable. The advantage of board is an 500Vdc isolation voltage is provided, and it can protect your PC system from damage when an abnormal input signal is occurred.

The ACLD-9185 is a 16 channel SPDT relay output board. This board is connected with CN2 of PCI-9111 via 20-pin flat cable. By using this board, you can control outside device through the digital output signals.

ACLD-9138 and ACLD-9188 are general purpose terminal boards for all the card which comes equipped with 37-pin D-sub connector. The ACLD-9138 has a LED indicator to show the power ON/OFF of your computer system.

The detail descriptions of the register format of the PCI-9111 are specified in this chapter. This information is quite useful for the programmer who wish to handle the card by low-level program. In addition, users can understand how to use software driver to manipulate this card after understanding the registers' structure of the PCI-9111.

The PCI-9111 functions as a 32-bit PCI target device to any master on the PCI bus. There are three types of registers on the PCI-9111: PCI Configuration Registers (PCR), Local Configuration Registers (LCR) and PCI-9111 registers.

The PCR which conforms the PCI-bus specifications is initialized and controlled by the system plug & play PCI BIOS. User‘s can study the PCI BIOS specification to understand the operation of the PCR.

The LCR is specified by the PCI bus controller PLX-9050. It is not necessary for users to understand the details of the LCR if you use the software library. The base address of the LCR is assigned by the PCI p&p BIOS. The assigned address is located at offset 14h of PCR.

The PCI-9111 registers are shown in the Table 4.1. The base address of the PCI-9111 registers is also assigned by the PCI p&p BIOS. The assigned base address is located at offset 18h of PCR. Therefore, users can read the PCR to know the PCI-9111 base address by using the BIOS function call. Note that the PCI-9111 registers are all 16 bits. The users can access these registers by 16 bits I/O instructions.

The PCI-9111 A/D data is stored in the FIFO after conversion. The data can be transferred to host memory by software only. The register format for 12 bits PCI-9111DG and 16 bits PCI-9111HR is bit-wise alignment but not fully compatible. For 12 bits PCI-9111 data, the 4 LSBs are used to memorized the channel number which the AD data is stored.

Attribute : read only

for 12-bits PCI-9111

for 16-bits PCI-9111HR

CH3 ~ CH0 : A/D channel number from which the data is derived.

The PCI-9111 provides 16 single-ended analog input channel. The channel control register is used to set the A/D channels to be converted. Under non-auto scanning mode, the register sets the channel number for conversion. Under auto-scanning mode, the register sets the ending channel number.

Attribute : write only

There are 8 bits in this register. The 4 LSBs (CN0~CN3) are used to select on-board multiplexer. Usually, only the 4 LSBs are used and 16 input channels can be selected. However, if there is an extension board which can provide extension ability to 256 analog input channels, the 4 MSBs (CN4~CN7) can also be used to control the extension board.

The AD channel setting can be read back from this register.

Attribute : read only

There are 8 bits in this register. Under non-auto scan mode, the 4 LSBs (CN0~CN3) show the channel number setting and the 4 MSBs (AS3~AS0) is all ‘0’. Under auto-scan mode, the 4LSBs record the ending channel number. The 4 MSBs is the selected channel, and the value will increase automatically if any A/D trigger signal is inserted.

The A/D range register is used to adjust the analog input ranges. This register directly controls the PGA (programmable gain amplifier). When a different gain value is set, the analog input range will be changed to the its corresponding value.

Attribute : write only

The relationship between gain setting and its corresponding A/D range is listed in the table below.

The A/D range setting and A/D FIFO status can be read back from this register.

Attribute : read only

This register is used to control the A/D trigger source and trigger method.

Attribute : write only

Only the modes listed below can be applied on the PCI-9111 card :

To generate a trigger pulse to the PCI-9111 for A/D conversion, you just write any data to this register, then the A/D converter will be triggered.

Attribute : write only

The PCI-9111 has dual interrupt systems and two interrupt sources can be generated and be checked by the software. This register is used to select the interrupt sources.

Attribute : write only

Because of the PCI interrupt signal is level trigger, the interrupt clear register must be written to clear the flag after processing the interrupt request event, otherwise another interrupt request will be inserted and cause the software hangs on processing the interrupt event.

Attribute : write only

The AD mode setting and interrupt control setting can be read from this register. Refer to section 4.7 and section 4.9 for the detailed definition of each bit.

Attribute : read only

The PCI-9111 provides four extended input signals and four extended output signals. The signals are on the 37 pin connector. The extended output signals can be read back from the high nibble of the extended input port.

Note that the output EDO pins on CN3 (37 pin connector) can be set as one of the following mode by software. The definition of the setting value can be found in header file of the library PCI9111.H.

The output EDO value can be put on the EDO pins only when the EDO mode is EDO mode 2. Under EDO mode 1, the output EDO value will not be put on the EDO pins, therefore the EDO signals are used as input only port. Under mode 3, the EDO pins presents the high nibble of the AD channel number no matter auto channel scan (ASCAN) bit is set or not.

Attribute : write only

Attribute : read only

There are 16 digital input channels and 16 digital output channels are provided by the PCI-9111. The address Base + 1C is used to access digital inputs and control digital outputs.

Attribute : read only

Attribute : write only

The D/A converter will convert the D/A output digital data to analog signal.

Attribute : write only

DA0 is the LSB and DA11 is the MSB of the 12 bits data.

--- : don't care

The 8254 occupies 4 I/O address locations in the PCI-9111 as shown blow. Users can refer to NEC's or Intel's data sheet for the full description of the 8254 features.

Attribute : read / write

To operate the PCI-9111, you can bypass the detailed register structures and use the high level application programming interface (API) to control your PCI-9111 card directly. The software libraries, DOS library for Microsoft C/C++ and Borland C/C++ are included in the Utility & Library diskette. Please refer to chapter 6 for more detailed information.

To operate the PCI-9111, users do not need to understand how to write a hardware dependent low-level program. The control of the PCI controller is complex and not described in the manual. We do not recommend users to program its applications based on low-level programming. If user does need to program in low-level programming, you can contact the dealer from whom you purchased the PCI-9111 for further PCI controller programming information.

The operation theorem of the functions on PCI-9111 card is described in this chapter. The functions include the A/D conversion, D/A conversion, Digital I/O and counter / timer. The operation theorem can help you to understand how to manipulate or to program the PCI-9111.

Before programming the PCI-9111 to perform the A/D conversion, you should understand the following issues:

For using the A/D converter, users must know about the property of the signal to be measured at first. The users can decide which channels to be used and connect the signals to the PCI-9111. Refer to the chapter 3 ‘ Signal Connection’ . In addition, users should define and control the A/D signal sources, including the A/D channel, A/D gain, and A/D signal types. Please refer to section 5.1.2. For A/D signal source control.

After deciding the A/D signal source, the user must decide how to trigger the A/D conversion and define/control the trigger source. The A/D converter will start to convert the signal to a digital value when a trigger signal is rising. Refer to the section 5.1.3 for the three trigger modes.

The A/D data should be transferred into PC's memory for further using or processing. The data can be either read by I/O instruction which is handled directly by software or transferred to memory via interrupt. Please refer to section 5.1.4 to obtain ideas about the multi-configurations for A/D data transferring.

Some applications need to grab the data only before or after special hardware event. The Pre-Trigger is useful to stop the A/D operation. Refer to section 5.1.5 for operation of pre-trigger mode.

To process A/D data, programmer should know about the A/D data format. Refer to section 5.1.6 for details.

To control the A/D signal source, the signal type, signal channel and signal range should be considered.

As ASCAN is set (1), the value in AD channel MUX register defines the ending channel number of auto-scanning operation. Under auto scan mode, the channel is scanning from channel 0 to the ending channel. Whenever a trigger signal is rising, the channel number to be selected will increase automatically. For example, if the ending channel number is 3, the auto channel scanning sequence is 0,1,2,3,0,1,2... , until the ASCAN bit is cleared.

The current A/D channel number could be read back from the A/D data register on 12 bits PCI-9111 DG but it is not possible to be read back for PCI-9111HR.

Note that the MUX register is 8 bits. The 4 LSBs is used to select the multiplxer on board. The 4 MSBs could be send out via the EDO pins of the CN3 connector to select the external daughter board. At most 16 daughter board can be selected and total 256 channels can be selected without extra circuits.

The available signal polarity on PCI-9111 is bi-polar but no uni-polar configuration. However, the bi-polar input range still covers the uni-polar applications. In addition the high resolution of the PCI-9111HR can cover the normal industry applications. Therefore, PCI-91111 is suitable for full range of applications.

The A/D conversion is starting by a trigger source, then the A/D converter will start to convert the signal to a digital value. In the PCI-9111, A/D conversion can be triggered by the Internal or External trigger source. The EITS bit of A/D control register is used to handle the internal or external trigger, please refer to section 4.7 for details. Whenever the external source is set, the internal sources are disable.

If the internal trigger is selected, two internal sources can be selected: the software trigger or the timer pacer trigger. The A/D operation mode is controlled by A/D mode bits (EITS, TPST) of A/D mode register. Total three trigger sources are provided in the PCI-9111. The different trigger conditions are specified as follows:

The trigger source is software controllable in this mode. That is, the A/D conversion is starting when any value is written into the software trigger register. This trigger mode is suitable for low speed A/D conversion. Under this mode, the timing of the A/D conversion is fully controlled by software. However, it is difficult to control the fixed A/D conversion rate unless another timer interrupt service routine is used to generate a fixed rate trigger. Refer to interrupt control section for fixed rate timer interrupt.

An on-board timer / counter chip 8254 is used to provide a trigger source for A/D conversion at a fixed rate. Two counters of the 8254 chip are cascaded together to generate trigger pulse with precise period. Please refer to section 5.5 for 8254 architecture. This mode is ideal for high speed A/D conversion. It can be combined with the FIFO half full interrupt or EOC interrupt to transfer data. It is also possible to use software FIFO polling to transfer data. The A/D trigger, A/D data transfer and Interrupt can be set independently, most of the complex applications can thus be covered.

It's recommend to use this mode if your applications need a fixed and precise A/D sampling rate.

Through the pin-17 of CN3 (ExtTrig), the A/D conversion also can be triggered by an external signal. The A/D conversion starts as ExtTrig changes from high to low. The conversion rate of this mode is more flexible than the previous two modes, because the users can handle the external signal by the outside device. The external trigger can be also combined with the FIFO half interrupt, EOC interrupt or program FIFO polling to transfer data.

The A/D data are buffered in the FIFO memory. The FIFO size on PCI-9111 is 1024 (1K) words. If the sampling rate is 100 KHz, the FIFO can buffer 10.24 ms analog signal. After the FIFO is full, the lasting coming data will be lost. The software must read out the FIFO data before it becomes full.

The data must be transferred to host memory after the date is ready and before the FIFO is full. On the PCI-9111, many data transfer modes can be used. The different transfer modes are specified as follows:

If the FIFO is empty before the A/D start, the FF_EF bit will be low. After the A/D is completed, the A/D data is written to FIFO immediately, therefore the FF_EF becomes high. You can consider the FF_EF bit as converted data ready status. That is, FF_EF is high means the data is ready. Note that, while A/D is converted, the ADBUSY bit is low. After A/D conversion, the ADBUSY become high to indicate not busy. Please do NOT use this bit to poll the AD data.

It is possible to read A/D converted data without polling. The A/D conversion time will not exceed 8.5m s on PCI-9111 card. Hence, after software trigger, the software can wait for at least 8.5m s then read the A/D register without polling.

The data polling transferring is very suitable for the application need to process AD data in real time. Especially when combining with the timer interrupt generation, the timer interrupt service routine can use the data polling method to get multi-channel A/D data in real time and under fixed data sampling rate.

ADlink recommend user to check your system to find out the user software‘s priority in the special application. If the application software is at the highest priority, to poll the FIFO every 10 ms is suitable. However, the user‘s program must check the FIFO is full or empty every time reading data.

To avoid this problem, the half-full polling method is used. If the A/D trigger rate is 100KHz, the FIFO will be half-full (512 words) in 5.12 ms. If the user‘s software checks the FIFO half full signal every 5 ms. When the FIFO is not half-full, the software does not read data, because it is difficult to know how much A/D data is stored in the FIFO and user must check the FIFO empty bit every time reading data. When the FIFO is full, the AD FIFO is overrun. This means the sampling rate is higher than users expect or the polling rate is too slow, it is also possible due to your system occupy the CPU resource thus reducing the polling rate . When the FIFO is half-full and not full, the software can read one "block" (512 words) A/D data without check the FIFO status. This method is very convenient to read A/D in size of a "block" and it is benefit to software programming.

Usually, the timer trigger is used under this mode, therefore the sampling rate is fixed. The method also utilizes the minimum CPU resources because it is not necessary to be highest priority. The other benefit is this method will not use hardware interrupt resource. Therefore, the interrupt is reserved for system clock or emergency external interrupt request. The FIFO half-full polling method is the most powerful A/D data transfer mode.

Under this mode, an interrupt signal is generated when FIFO become half-full, that means there are 512 words data in the FIFO already. The ISR can read a block of data at every interrupt occurring. This method is very convenient to read A/D in size of a "block" (512 words) and it is benefit for software programming.

In certain applications, the data acquisition is applied and stops under special hardware signal. Without pre-trigger function, the software can start the A/D at any time, but it is every difficult to stop the A/D in real-time by software. Under "Pre-Trigger" mode, the pre-trigger (PTRG) signal and the 8254 counter 0 are used to "STOP" the A/D sampling.

After the external pre-trigger signal is inserted, the 8254 counter 0 is started to count number of the A/D conversion trigger signal. After set up the pre-trigger mode, the hardware is continuously acquiring A/D data and waiting for the PreTrig signal. Before the Pre-Trigger is inserted, the software must read the FIFO data to prevent the FIFO full. If these data are usable, the software can store these data as many as possible to the host PC‘s memory.

When the Pre-Trigger signal is inserted, the counter is starting to count down from the initial counter value N. The A/D trigger will be disable automatically when the counter value reach zero. The value of N could be 1 to 65535 and the last N A/D data is sampled after the Pre-Trigger signal. The software must continuously read data out from the FIFO to prevent FIFO full. The software also should poll the counter value to check if the A/D sampling is stopped.

To set up the pre-trigger mode, the following step should be following:

The Pre-trigger timing is shown as following: